Work Function Layer Patterning With Hard Mask Dielectric Protection
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, the challenge arises in precisely patterning work function layers without damaging the gate dielectric layer, which is crucial for controlling threshold voltage and metal gate height in FinFET devices.
Innovation Solution
A method involving a first hard mask layer over the work function layer, with a photoresist including a bottom anti-reflective coating (BARC) layer, allows for precise patterning using wet etching to minimize damage to the gate dielectric layer and reduce metal gate deformation, employing a tri-layer photoresist and specific etching processes to control the etching of the work function layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional lithography patterning is used on work function layer, then metal gate height can be controlled, but gate dielectric layer is damaged
Solution Approach 1:
A hard mask layer is introduced as an intermediary between the work function layer and the gate dielectric layer. This hard mask layer absorbs the etching damage that would otherwise directly affect the gate dielectric layer, allowing precise patterning of the work function layer while protecting the underlying dielectric structure from damage
Solution Approach 2:
The patterning process is segmented into multiple stages: first patterning the hard mask layer, then using it as a mask to pattern the work function layer. This segmentation allows the etching process to be performed on the harder, more damage-resistant hard mask material first, before transferring the pattern to the work function layer with minimal dielectric damage
2Productivity
If feature size is reduced to increase integration density, then more components can be integrated, but patterning precision and damage control become more difficult
Solution Approach 1:
The patent replaces direct lithography patterning on the work function layer with an indirect patterning approach using wet etching through a hard mask layer. This substitution allows for better control at reduced feature sizes by using the hard mask layer as a protective intermediary that can be precisely patterned and then transferred to the work function layer with minimal damage
Solution Approach 2:
The hard mask layer is deposited and patterned in advance before the work function layer patterning. This preliminary action creates a protective template that guides the subsequent work function layer etching, ensuring precise patterning at reduced feature sizes while preventing damage to the gate dielectric layer during the etching process
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enables precise control of the work function layer patterning, minimizing damage to the gate dielectric layer, allowing for fine-tuning of threshold voltage and metal gate height, while reducing deformation and width changes during the patterning process.
Implementation Method 1
The first hard mask layer is used to protect the work function layer and the gate dielectric layer during the etching of the subsequently deposited bottom anti-reflective coating (BARC) layer over the first hard mask layer
Data Source
AI summary
A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.