Work Function Layer Recessing for Integrated Circuit Gate Width Control

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Solution Overview

Problem

Current integrated circuit manufacturing processes require multiple lithographic steps to form replacement metallic gates of varying widths, which are costly and inefficient.

Innovation Solution

The method involves forming a work function layer over a substrate with dielectric columns, recessing it in long and short regions without lithography, and forming a replacement metallic gate, reducing the need for lithographic processes by using organic layers and sacrificial layers to control the height of the work function layer.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If multiple lithographic processes are used to form replacement metallic gates of varying widths, then manufacturing precision is improved, but production cost increases

Engineering Contradiction:
Improvewidth control of replacement metallic gatesVSAvoidproduction cost
Core Design Contradiction:
Manufacturing precisionVSEase of manufacture

Solution Approach 1:

The patent forms a common work function layer over all dielectric columns before recessing operations. This preliminary formation allows subsequent selective recessing to create different gate widths without requiring separate lithographic steps for each width variation, thereby reducing production costs while maintaining precision

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent segments the work function layer recessing process into different regions (first regions and second regions) with different target heights. By defining first work function heights for some dielectric columns and second work function heights for others, the method achieves varied gate widths through a single lithographic process followed by selective recessing, eliminating the need for multiple lithographic steps

Inventive Principle:
Principle #1Segmentation

2Reliability

If replacement metallic gate is recessed to increase dielectric barrier distance, then reliability is improved, but manufacturing complexity increases

Engineering Contradiction:
Improveelectrical insulation between gate and contactVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent applies different recess depths to different regions: work function layers over first dielectric columns are recessed to first heights providing greater dielectric barrier distance, while work function layers over second dielectric columns are recessed to second heights. This local differentiation achieves enhanced reliability where needed without unnecessarily complicating the entire manufacturing process

Inventive Principle:
Principle #3Local quality

3Manufacturing precision

If different processes are used for recessing replacement metallic gates in short and long regions, then manufacturing precision is improved, but productivity decreases

Engineering Contradiction:
Improvewidth differentiation between short and long regionsVSAvoidproduction efficiency
Core Design Contradiction:
Manufacturing precisionVSProductivity

Solution Approach 1:

The patent uses a single lithographic process to define both short regions and long regions, and a unified recessing process to create different work function heights in both region types. This multi-functional approach achieves width differentiation without requiring separate process sequences for short and long regions, thereby maintaining high productivity

Inventive Principle:
Principle #6Universality (Multi-functionality)

Data Source

PatentUS9583584B2Methods for producing integrated circuits using long and short regions and integrated circuits produced from such methods
Publication Date: 2017.02.28 GLOBALFOUNDRIES US INC
  • US9583584B2 patent drawing
  • US9583584B2 patent drawing
  • US9583584B2 patent drawing

AI summary

Integrated circuits and methods for producing the same are provided. In an exemplary embodiment, a method for producing an integrated circuit includes forming a work function layer overlying a substrate and a plurality of dielectric columns. The dielectric columns and the substrate define a short region having a short region width and a long region having a long region width greater than the short region width. The work function layer is recessed in the long region to a long region work function height that is between a dielectric column top surface and a substrate top surface. The work function layer is also recessed in the short region to a short region work function height that is between the dielectric column top surface and the substrate top surface. Recessing the work function layer in the long and short regions is conducted in the absence of lithography techniques.