Work Function Metal Gate Filling via Anti-Reflective Layer

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Solution Overview

Problem

Conventional gate last processes in semiconductor manufacturing face challenges in filling the gate trench with work function metal layers due to reduced opening widths, leading to metal gate void issues and deteriorated electrical performance.

Innovation Solution

A method involving the formation of a substrate with complementary transistors, an inner-layer dielectric layer, and a work function metal layer, followed by the application and selective removal of an anti-reflective layer to create U-shaped and L-shaped metal layers in specific gate trenches, allowing for improved metal filling without the need for additional anti-reflective layer processes.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If barrier layer or strained stress layer is formed in the gate trench before forming the metals, then the gate trench opening width is reduced, but it becomes difficult to fill the gate trench with the work function metal layer causing metal gate void issue

Engineering Contradiction:
Improvegate metal filling qualityVSAvoidgate trench opening width
Core Design Contradiction:
ReliabilityVSLength of moving object

Solution Approach 1:

The patent applies preliminary action by forming the work function metal layer before depositing the anti-reflective layer. This sequence allows the metal layer to be deposited when the gate trench opening is still wide enough for complete filling, preventing metal gate voids. The anti-reflective layer is then deposited to protect the metal layer and enable subsequent photolithography processes.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent changes the deposition sequence parameter - instead of the conventional approach where barrier/stress layers are formed first followed by metal layers, this patent deposits the work function metal layer first, then the anti-reflective layer. This parameter change in the layer formation sequence resolves the filling issue by ensuring the metal layer is deposited when maximum trench accessibility is available.

Inventive Principle:
Principle #35Parameter changes

2Adaptability or versatility

If conventional gate last process is used, then material choices for high-K gate dielectric layer and metal gate are wider, but barrier layer or strained stress layer formation reduces gate trench opening width

Engineering Contradiction:
Improvematerial choicesVSAvoidgate trench opening width
Core Design Contradiction:
Adaptability or versatilityVSLength of moving object

Solution Approach 1:

The patent maintains the gate last process advantages of material versatility while applying preliminary action by depositing the work function metal layer before the anti-reflective layer. This ensures the metal layer is formed when the gate trench is still accessible, preventing filling issues while preserving the ability to choose from various high-K dielectric and metal gate materials.

Inventive Principle:
Principle #10Preliminary action

3Reliability

If additional anti-reflective layer coating and removal processes are implemented, then metal gate filling is improved, but manufacturing process complexity increases

Engineering Contradiction:
Improvemetal gate fillingVSAvoidmanufacturing process steps
Core Design Contradiction:
ReliabilityVSDevice complexity

Solution Approach 1:

The patent merges the anti-reflective layer deposition with the existing manufacturing process flow. The anti-reflective layer is deposited over the work function metal layer in the same process sequence, and its selective removal is integrated with the photolithography patterning steps. This merging approach improves metal gate filling without adding significant process complexity, as the anti-reflective layer serves dual purposes: protecting the metal layer and enabling photolithography alignment.

Inventive Principle:
Principle #5Merging (Combining)

Data Source

PatentUS9305847B2Method of manufacturing semiconductor device having gate metal
Publication Date: 2016.04.05 UNITED MICROELECTRONICS CORP
  • US9305847B2 patent drawing
  • US9305847B2 patent drawing
  • US9305847B2 patent drawing

AI summary

A method of manufacturing a semiconductor device is provided. The method includes the following steps. A substrate including a first transistor having a first conductivity type, a second transistor having a second conductivity type and a third transistor having the first conductivity type is formed. An inner-layer dielectric layer is formed on the substrate, and includes a first gate trench corresponding to the first transistor, a second gate trench corresponding to the second transistor and a third gate trench corresponding to the third transistor. A work function metal layer is formed on the inner-layer dielectric layer. An anti-reflective layer is coated on the work function metal layer. The anti-reflective layer on the second transistor and on the top portion of the third gate trench is removed to expose the work function metal layer. The exposed work function metal layer is removed.