Work Function Metal Gate Composition for Nano-FET Scaling
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Solution Overview
Problem
As semiconductor devices continue to shrink in feature size, challenges arise in integrating more components into smaller areas, requiring innovative manufacturing processes to maintain performance and efficiency, particularly in the formation of nano-FETs and FinFETs.
Innovation Solution
The use of advanced manufacturing techniques such as gate-all-around transistor structures, epitaxial source/drain regions, and atomic layer deposition (ALD) processes to form work function metal layers with specific compositions and oxygen concentrations, enabling precise tuning of the work function and improving device performance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If minimum feature sizes are reduced to increase integration density, then more components can be integrated into a given area, but patterning and fabrication challenges increase
Solution Approach 1:
The patent applies segmentation by dividing the patterning process into multiple stages through double-patterning and multi-patterning techniques. Instead of attempting to create all features in a single lithography step, the process segments pattern formation into sequential steps, where each step creates a subset of the final pattern. This allows achieving higher integration density with controllable manufacturing precision at each stage.
Solution Approach 2:
The patent transitions from two-dimensional planar transistors to three-dimensional structures including FinFETs with vertical fins and GAA transistors with vertical nanosheets/channels. This dimensional change from 2D to 3D enables increased integration density by utilizing the vertical dimension for current conduction while maintaining smaller pitch sizes in the lateral dimension.
2Quantity of substance
If pitch sizes are reduced to increase integration density, then more devices fit in a given area, but fabrication and material deposition challenges increase
Solution Approach 1:
The patent employs preliminary action through self-aligned processes where mandrels and spacers are formed in specific sequences to pre-position structures for subsequent steps. The mandrel formation and spacer deposition are performed beforehand to establish precise alignment references, eliminating the need for additional alignment operations and reducing fabrication complexity despite smaller pitch sizes.
Solution Approach 2:
The patent applies self-service through self-aligned patterning where previously formed structures (mandrels, spacers) automatically serve as alignment references for subsequent patterning steps. The spacer material itself defines the position of future features without requiring external alignment tools, enabling reduced pitch sizes with manageable fabrication complexity.
3Manufacturing precision
If photolithography and self-aligned processes are used to create nanostructures, then precise feature formation is achieved, but process steps and manufacturing complexity increase
Solution Approach 1:
The patent merges multiple functions into integrated process steps. For example, the same spacer formation process serves both as a patterning step and as a structural formation step for the final device. The mandrel structures serve dual purposes as both alignment references and eventual device components that may be retained or transformed, reducing the total number of discrete process steps while maintaining manufacturing precision.
Solution Approach 2:
The patent applies universality by designing process steps that perform multiple functions. The spacer deposition process universally serves as both a patterning mechanism and a structural formation step. The same material layers and deposition techniques are used across different device regions and structure types, standardizing the process and managing complexity despite the precision requirements.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
Enhances the integration density and performance of semiconductor devices by allowing for precise control of the work function and strain distribution, leading to improved current flow and reduced defects in nano-FETs and FinFETs.
Implementation Method 1
atomic layer deposition (ALD) processes to form work function metal layers with specific compositions and oxygen concentrations
Implementation Method 2
enabling precise tuning of the work function and improving device performance
Data Source
AI summary
A semiconductor device includes source and drain regions, a channel region between the source and drain regions, and a gate structure over the channel region. The gate structure includes a gate dielectric over the channel region, a work function metal layer over the gate dielectric and comprising iodine, and a fill metal over the work function metal layer.