Work Function Layer Patterning to Protect FinFET Gate Dielectrics

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Solution Overview

Problem

As semiconductor devices continue to shrink in feature size, the integration density of electronic components increases, but this leads to challenges in minimizing damage to gate dielectric layers during the patterning of work function layers, which affects the threshold voltage and metal gate deformation in FinFET devices.

Innovation Solution

A method involving a first hard mask layer over the work function layer, with a photoresist including a bottom anti-reflective coating (BARC) layer, is used to protect the gate dielectric layer during etching, allowing for precise patterning of the work function layer using a wet etching process, minimizing damage and enabling precise control of metal gate height and threshold voltage.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Quantity of substance

If feature size is reduced to increase integration density, then more components can be integrated into a given area, but damage to gate dielectric layer during patterning increases

Engineering Contradiction:

Improveintegration densityVSAvoiddamage to gate dielectric layer

Core Design Contradiction:

Quantity of substanceVSObject-affected harmful factors

Solution Approach 1:

The photoresist is divided into multiple layers (first photoresist layer and second photoresist layer) with different functions. The first layer provides pattern definition while the second layer protects the gate dielectric layer during etching, allowing feature size reduction without increasing damage to underlying layers.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

A bottom anti-reflective coating (BARC) layer is introduced as an intermediary between the photoresist and the gate dielectric layer. This BARC layer absorbs excess energy during etching and prevents direct damage to the gate dielectric, enabling safer patterning at smaller feature sizes.

Inventive Principle:

Principle #24Intermediary (Mediator)

2Manufacturing precision

If work function layer is precisely patterned to control threshold voltage, then device performance is improved, but metal gate deformation increases

Engineering Contradiction:

Improvepatterning precision of work function layerVSAvoidmetal gate deformation

Core Design Contradiction:

Manufacturing precisionVSShape

Solution Approach 1:

The protective photoresist structure is formed and positioned before the etching process begins. This preliminary protective layer prevents metal gate deformation during subsequent etching operations, allowing precise patterning of the work function layer without compromising gate integrity.

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The second photoresist layer and BARC layer are deposited beforehand to create a cushioning effect during etching. These layers absorb mechanical and thermal stress that would otherwise cause metal gate deformation, enabling precise work function layer patterning while maintaining gate shape stability.

Inventive Principle:

Principle #11Beforehand cushioning (Prior cushioning)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This approach effectively minimizes damage to the gate dielectric layer, reduces metal gate deformation, and allows for precise patterning of the work function layer, enhancing the performance and reliability of FinFET devices by fine-tuning the threshold voltage and controlling metal gate height.

Implementation Method 1

depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer

Methodology Applied

Scientific EffectAnti-reflective coating: Anti-Reflective Coating

Implementation Method 2

etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer

Methodology Applied

Scientific EffectWet etching:

Data Source

PatentUS20240063060A1Patterning method and structures resulting therefrom

Publication Date: 2024.02.22 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD

AI summary

A method includes depositing a first work function layer over a gate dielectric layer, forming a first hard mask layer over the first work function layer, forming a photoresist mask over the first hard mask layer, where forming the photoresist mask includes depositing a bottom anti-reflective coating (BARC) layer over the first hard mask layer, etching a portion of the BARC layer, etching a portion of the first hard mask layer using the BARC layer as a mask, etching a portion of the first work function layer to expose a portion of the gate dielectric layer through the first hard mask layer and the first work function layer, removing the first hard mask layer, and depositing a second work function layer over the first work function layer and over the portion of the gate dielectric layer.