Workfunction Metal Stack Uniformity in HKMG Gate Formation
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Solution Overview
Problem
In high-K metal gate (HKMG) gate first technologies, the challenge lies in controlling the thickness of nMOS and pMOS workfunction metal stacks, leading to uneven final metal gate topologies unsuitable for gate etching and manufacturing.
Innovation Solution
A method is introduced where a hardmask is used to protect the pMOS workfunction stack during the deposition and removal of the nMOS workfunction stack, ensuring both stacks have substantially equal thicknesses, involving specific layer formations and etching processes to achieve uniformity.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional processes are used to form nMOS and pMOS workfunction metal stacks with different thicknesses, then the workfunction requirements for each transistor type are met, but the final metal gate topology becomes uneven and unsuitable for gate etching and manufacturing
Solution Approach 1:
A hardmask layer is formed over the pMOS workfunction metal stack before the nMOS workfunction metal deposition process. This preliminary protective action prevents nMOS metal from depositing on the pMOS stack, ensuring that subsequent etching processes can proceed uniformly across both transistor types without damaging the pMOS structure.
Solution Approach 2:
The hardmask layer serves as an intermediary protective barrier between the nMOS workfunction metal deposition/etching processes and the pMOS workfunction metal stack. This intermediary layer allows the nMOS processing to occur without directly affecting the pMOS stack, enabling uniform gate topology while maintaining different workfunction thicknesses.
2Manufacturing precision
If the nMOS and pMOS workfunction metal stacks are removed and reformed to achieve equal thickness, then the gate topology becomes uniform, but the workfunction setting capability is compromised
Solution Approach 1:
The hardmask is formed preliminarily over the pMOS workfunction stack before nMOS metal deposition. This allows the nMOS workfunction metal to be deposited to the correct thickness without being limited by the need to protect the pMOS stack through removal and reforming processes, thereby maintaining workfunction setting capability while achieving uniform topology.
Solution Approach 2:
The hardmask acts as an intermediary that decouples the topology uniformity requirement from the workfunction setting process. By protecting the pMOS stack during nMOS processing, the hardmask enables independent optimization of both the pMOS and nMOS workfunction thicknesses while ensuring the final gates have uniform topology suitable for etching.
3Ease of manufacture
If the pMOS workfunction metal stack is removed to allow nMOS metal deposition, then the nMOS gate can be formed, but the pMOS workfunction stack is damaged and requires protective measures
Solution Approach 1:
The hardmask layer serves as a protective intermediary between the nMOS fabrication processes and the pMOS workfunction metal stack. During nMOS workfunction metal deposition and etching, the hardmask prevents direct contact and potential damage to the pMOS stack, allowing straightforward nMOS gate formation while preserving the pMOS structure.
Solution Approach 2:
The hardmask is formed in advance over the pMOS workfunction stack before any nMOS processing occurs. This preliminary protective measure ensures that subsequent nMOS gate formation steps can proceed without concern for pMOS stack damage, simplifying the manufacturing process while protecting sensitive structures.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach results in a final metal stack with excellent workfunction setting and high manufacturability, enabling the formation of semiconductor devices with consistent and suitable gate topologies.
Implementation Method 1
protecting the pMOS workfunction stack with a hardmask during deposition and removal of the nMOS workfunction stack
Implementation Method 2
annealing the pMOS and nMOS workfunction metal stack layers at a temperature of 800° C. to 950° C. subsequent to removing the hardmask layer
Implementation Method 3
forming a pMOS workfunction metal stack layer on the n-type area and the p-type area
Implementation Method 4
wet etching
Implementation Method 5
dry etching the SiN
Data Source
AI summary
Transistor devices are formed with a pMOS and an nMOS workfunction stack of substantially equal thickness after gate patterning. Embodiments include forming n-type and p-type areas in a substrate, forming a pMOS workfunction metal stack layer on both areas, forming a hardmask layer on the pMOS workfunction metal stack layer on the n-type area, removing the pMOS workfunction metal stack layer from the p-type area, forming an nMOS workfunction metal stack layer on the p-type area and on the hardmask layer, and removing the nMOS workfunction metal stack layer from the hardmask layer.