Working Digital Perceptron Parallel Processing Energy Efficiency
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Solution Overview
Problem
Existing digital computing systems, such as Von Neumann architecture, face inefficiencies in energy consumption and processing time due to sequential logic computations, whereas biologic nerve systems excel in parallel processing and energy efficiency through neuromorphic structures.
Innovation Solution
A digital in-memory processor, named Working Digital Perceptron (WDP), utilizing fast-write and high-endurance latch-type volatile memory cells in Content Addressable Memory (CAM) and Static Random Access Memory (SRAM) arrays for parallel processing, mimicking the brain's working memory functionality.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If sequential logic computations are used in Von Neumann architecture, then processing can be completed with standard CPU architecture, but energy consumption increases and processing time extends
Solution Approach 1:
The patent replaces the mechanical sequential logic computation system with a content-addressable memory-based parallel processing system. The CAM array performs parallel pattern matching operations without traditional CPU logic units, eliminating the need for sequential instruction execution and reducing energy consumption associated with clock-synchronized operations across multiple logic gates.
Solution Approach 2:
The patent segments the processing function into distinct memory components: CAM array for parallel pattern matching, SRAM arrays for storing content symbols and response symbols, and dedicated output circuits. This segmentation allows each component to operate independently and in parallel, avoiding the sequential bottlenecks of traditional CPU architecture while maintaining ease of manufacture through standardized memory cell designs.
2Ease of manufacture
If sequential logic computations are used in Von Neumann architecture, then standard CPU architecture can be maintained, but processing time increases
Solution Approach 1:
The patent segments the processing function into distinct memory components: CAM array for parallel pattern matching, SRAM arrays for storing content symbols and response symbols, and dedicated output circuits. This segmentation allows each component to operate independently and in parallel, avoiding the sequential bottlenecks of traditional CPU architecture.
Solution Approach 2:
The patent performs preliminary action by pre-storing content symbols and response symbols in the CAM and SRAM arrays during system initialization or learning phases. This allows the processing stage to simply perform parallel pattern matching without requiring sequential computation, dramatically reducing processing time while maintaining architectural simplicity.
3Productivity
If volatile memory cells are used for rapid updates, then information processing environments can be rapidly updated, but data retention capability decreases
Solution Approach 1:
The patent applies dynamics by making the memory system adaptable to different operational modes. The volatile memory cells can be rapidly written during learning or update phases when productivity is prioritized, and then maintain stable readings during processing phases where data retention is sufficient for the duration of computation. This dynamic usage pattern allows the system to optimize for speed when needed while accepting temporary data retention limitations.
Solution Approach 2:
The patent performs preliminary action by loading all necessary content symbols and response symbols into the volatile memory arrays before processing begins. This pre-loading ensures that during the actual processing phase, the data remains stable and unchanged, effectively managing the data retention requirement without compromising update speed when data needs to be modified.
Data Source
AI summary
A dynamic digital perceptron device is disclosed. The dynamic digital perceptron device of the invention comprises a volatile content memory array, a detection and driver circuit and a volatile response memory array. The dynamic digital perceptron device processes input digital information according to a database of the digital content data stored in the volatile content memory array and outputs the correspondent digital data stored in the volatile response memory array by the detection and driver circuit. Moreover, the volatile content memory array and the volatile response memory array in the dynamic digital perceptron device are constructed by the latch-types of memory cells to handle the rapid and frequent changing digital processing environments.