Working Global History Register for Branch Prediction Accuracy
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Solution Overview
Problem
Conventional processors face inaccuracies in branch predictions due to delayed updating of branch history information, leading to mispredictions and performance issues when multiple branch instructions are executed in a short period.
Innovation Solution
A processor design that identifies branch instructions early in the execution stages and uses a Working Global History Register (WGHR) to load and process branch history information in multiple stages, ensuring more accurate predictions by utilizing current branch history for subsequent conditional branch instructions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Measurement precision
If branch history information is updated only after deep pipeline evaluation, then the processor pipeline can maintain simpler structure and faster clock speed, but branch prediction accuracy deteriorates leading to mispredictions and performance loss
Solution Approach 1:
The patent applies preliminary action by updating the branch history register earlier in the pipeline (at the evaluation stage) rather than waiting until deep pipeline completion. This allows the branch history to be available sooner for subsequent branch predictions, improving accuracy without requiring pipeline stalls. The working branch history register captures branch outcomes at an intermediate point, enabling earlier use of this information for prediction purposes.
2Measurement precision
If a single branch history register is used updated at decode stage, then device complexity is reduced, but branch prediction accuracy deteriorates when multiple branch instructions are executed in parallel
Solution Approach 1:
The patent segments the branch history updating mechanism into two distinct paths: one for updating at the decode stage and another for updating at the evaluation stage. The working branch history register is selectively updated based on which stage detects the branch instruction first. This segmentation allows the system to maintain accurate branch history for parallel branch instructions without requiring a completely complex redesign of the register update mechanism.
Solution Approach 2:
The patent introduces dynamic behavior by making the branch history register update timing flexible rather than fixed. The register can be updated at different pipeline stages depending on when the branch instruction is detected. This dynamic updating approach allows the system to adapt to different execution scenarios and maintain accuracy without requiring static complex update mechanisms for all possible cases.
3Productivity
If branch history is updated later in the pipeline, then power consumption is reduced, but misprediction rate increases causing performance degradation
Solution Approach 1:
The patent applies partial action by implementing selective updating of the working branch history register only when branch instructions are detected at specific pipeline stages. Rather than continuously updating the register at every cycle or for every instruction, the system updates only when necessary (when a branch is detected). This partial updating approach maintains prediction accuracy for critical branches while reducing unnecessary power consumption from continuous register writes.
Data Source
AI summary
A method of processing branch history information is disclosed. The method retrieves branch instructions from an instruction cache and executes the branch instructions in a plurality of pipeline stages. The method verifies that a branch instruction has been identified. The method further receives branch history information during a first pipeline stage and loads the branch history information into a first register. The method further loads the branch history information into the second register during the second pipeline stage.