Workload-Aware VM Pause Delays for P- and E-Core Efficiency

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Solution Overview

Problem

Existing virtual machine (VM) systems with statically set maximum pause delays for the TPAUSE instruction fail to account for the nuances of hybrid architectures combining Performance-cores (P-cores) and Efficiency-cores, leading to non-optimal polling times and increased power consumption, resulting in performance and efficiency losses.

Innovation Solution

The processor capabilities manager dynamically adjusts core C-states and maximum pause delay durations in real-time based on metrics such as host system idle and utilization rates, energy-performance preference, system workload profiles, and thermal limitations to optimize polling times and core power states.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Use of energy by moving object

If a static maximum pause delay is set for the TPAUSE instruction, then the system configuration is simple and stable, but the polling time is non-optimal and power consumption increases

Engineering Contradiction:
Improvepower consumptionVSAvoidconfiguration complexity
Core Design Contradiction:
Use of energy by moving objectVSDevice complexity

Solution Approach 1:

The patent applies dynamics by transitioning from a static maximum pause delay configuration to a dynamic one that automatically adjusts based on real-time host system conditions. The processor capabilities manager monitors metrics such as idle rates, utilization rates, energy-performance preferences, workload profiles, and thermal limitations to dynamically modify the pause delay duration. This dynamic adjustment allows the system to optimize polling times according to actual operational state, reducing unnecessary power consumption while adapting to varying workload conditions without requiring manual reconfiguration.

Inventive Principle:
Principle #15Dynamics

2Productivity

If a static maximum pause delay is used, then the system operation is simple, but processing performance on hybrid platforms is non-optimal

Engineering Contradiction:
Improveprocessing performanceVSAvoidoperation simplicity
Core Design Contradiction:
ProductivityVSEase of operation

Solution Approach 1:

The patent implements feedback mechanisms where the processor capabilities manager continuously monitors host system metrics including idle rates, utilization rates, energy-performance preferences, workload profiles, and thermal limitations. Based on this feedback, the system automatically adjusts the maximum pause delay duration to optimize processing performance on hybrid architectures combining Performance-cores and Efficiency-cores. This feedback-driven adaptation ensures that polling times are optimized for current system conditions, improving productivity while maintaining ease of operation through automated management.

Inventive Principle:
Principle #23Feedback

3Measurement precision

If the pause delay is extended to improve polling accuracy, then measurement precision improves, but loss of time increases

Engineering Contradiction:
Improvepolling accuracyVSAvoidtime wasted on VM Exit events
Core Design Contradiction:
Measurement precisionVSLoss of time

Solution Approach 1:

The patent applies parameter changes by dynamically modifying the maximum pause delay duration based on real-time system conditions. The processor capabilities manager adjusts this critical parameter according to monitored metrics such as idle rates, utilization rates, energy-performance preferences, workload profiles, and thermal limitations. This dynamic parameter adjustment allows the system to optimize the balance between polling accuracy and time efficiency, extending the pause delay only when necessary to achieve accurate polling while minimizing time wasted on VM Exit events during high-performance windows.

Inventive Principle:
Principle #35Parameter changes

Data Source

PatentUS20250284521A1Methods and apparatus to dynamically configure delay durations and/or core power states in virtual computing environments
Publication Date: 2025.09.11 INTEL CORP
  • US20250284521A1 patent drawing
  • US20250284521A1 patent drawing
  • US20250284521A1 patent drawing

AI summary

A disclosed example accesses a workload type indicator associated with a workload executed on a virtual machine hosted by an apparatus; and sets a delay duration in a configuration register. the delay duration based on at least one of the workload type indicator or a temperature measurement value corresponding to hardware.