Workload Scheduling Based on Detected Hardware Errors
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Solution Overview
Problem
In logical partitioned data processing systems, hardware errors such as cache and interconnect errors can lead to suboptimal processor performance and potential downtime, as existing scheduling methods do not consider these errors when allocating workloads.
Innovation Solution
The system determines the nature and impact of hardware errors and schedules workloads on different processor cores or processors to avoid using faulty cache lines or interconnects, utilizing partition management firmware to track and manage errors and allocate resources optimally.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If workloads are scheduled without considering hardware errors, then processor utilization is maximized, but system reliability deteriorates due to potential downtime from hardware errors
Solution Approach 1:
The patent segments the processor into multiple cores and further segments the cache hierarchy into private and shared components. When hardware errors are detected in specific cache lines or cores, only those specific segments are isolated or migrated away from, while the rest of the processor continues to operate at full capacity. This selective segmentation maintains high processor utilization while ensuring system reliability.
Solution Approach 2:
The patent implements preliminary error detection and classification mechanisms that identify hardware errors before they cause system failures. The system proactively monitors cache errors, interconnect errors, and core errors, and preemptively migrates workloads or isolates affected components. This preliminary action prevents downtime while maintaining optimal processor utilization.
2Reliability
If workloads are migrated frequently to avoid hardware errors, then system reliability is maintained, but processor performance deteriorates due to migration overhead
Solution Approach 1:
The patent applies local quality by making migration decisions based on the specific location and type of hardware error. Instead of migrating workloads globally or frequently, the system only migrates workloads from specifically affected cores or cache lines. The migration policy adapts to the local error conditions, migrating only when necessary and only for the minimum required duration, thereby maintaining system availability while minimizing performance impact.
Solution Approach 2:
The patent implements partial migration strategies where only the portions of workloads affected by hardware errors are migrated, while other portions continue to execute on the original processor. The system performs selective migration based on error severity and type, avoiding excessive full-workload migrations. This partial action maintains system availability while reducing the performance overhead associated with complete workload migrations.
3Speed
If private cache is used to improve performance, then processor speed is enhanced, but reliability deteriorates when cache errors occur
Solution Approach 1:
The patent implements dynamic workload migration policies that respond to real-time cache error conditions. When cache errors are detected in private cache, the system dynamically decides whether to migrate the workload to a different core with healthy cache or to use shared cache resources. The migration decision is based on the severity and persistence of cache errors, allowing the system to maintain high processor speed during normal operation while ensuring workload execution reliability when cache errors occur.
Data Source
AI summary
Scheduling workloads based on detected hardware errors is provided. In response to determining that a hardware error is detected, it is determined whether the hardware error is a cache error. In response to determining that the hardware error is a cache error, it is determined whether execution of a workload on a processor is changing contents of a cache associated with the cache error more than a threshold value. In response to determining that the execution of the workload on the processor is changing the contents of the cache associated with the cache error more than the threshold value, it is determined whether the cache associated with the cache error is private to a core in the processor. In response to determining that the cache associated with the cache error is private to a core, the execution of the workload is scheduled on a different core of the processor.