Main Memory Access via Workload-Switched Hierarchy and FIFO Paths
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Solution Overview
Problem
Existing compute devices are limited in performance by memory hierarchies that inefficiently handle both compute-intense and memory-intense workloads, particularly memory-intense workloads due to frequent traversal through multiple levels, which increases time and power consumption.
Innovation Solution
A compute device with two paths for data and instruction transfer: a memory hierarchy path for compute-intense workloads and a FIFO buffer path for memory-intense workloads, controlled by switch circuitry that determines workload type for efficient data transfer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a memory hierarchy is used for data transfer, then compute-intense workloads benefit from faster access, but memory-intense workloads suffer from frequent traversal through multiple levels increasing time and power consumption
Solution Approach 1:
The patent segments the data transfer path into two distinct routes: a memory hierarchy path for compute-intense workloads and a FIFO buffer path for memory-intense workloads. This segmentation allows each path to be optimized for its specific workload type, resolving the contradiction by preventing memory-intense workloads from traversing multiple memory levels while still providing fast access for compute-intense workloads.
Solution Approach 2:
The patent implements dynamic switching between the memory hierarchy path and the FIFO buffer path based on workload characteristics. The system dynamically adapts the data transfer route according to whether the current workload is compute-intense or memory-intense, thereby optimizing performance while minimizing unnecessary time loss from frequent memory level traversals.
2Productivity
If a memory hierarchy is used for data transfer, then compute-intense workloads achieve better performance, but power consumption increases due to frequent traversal through multiple levels
Solution Approach 1:
The patent divides the data transfer infrastructure into separate paths: a memory hierarchy path for compute-intense workloads and a FIFO buffer path for memory-intense workloads. This segmentation prevents memory-intense workloads from consuming excessive power by avoiding frequent traversals through multiple memory levels, while still enabling fast performance for compute-intense workloads.
Solution Approach 2:
The system dynamically selects between the memory hierarchy path and FIFO buffer path based on workload type. By adapting the data transfer route in real-time, the system minimizes power consumption during memory-intense operations while maintaining high performance during compute-intense operations, thus resolving the contradiction between productivity and energy usage.
3Adaptability or versatility
If a single data transfer path is used, then device complexity is reduced, but the system cannot efficiently handle both compute-intense and memory-intense workloads
Solution Approach 1:
The patent segments the data transfer system into two specialized paths: a memory hierarchy path optimized for compute-intense workloads and a FIFO buffer path optimized for memory-intense workloads. This segmentation enables the system to handle both workload types efficiently while keeping each path's structure relatively simple and purpose-specific.
Solution Approach 2:
The patent creates a universal data transfer system that can accommodate both compute-intense and memory-intense workloads by providing multiple paths. The switch circuitry enables a single system to serve multiple workload types, achieving versatility without requiring entirely separate systems for each workload category.
Data Source
AI summary
Systems, apparatus, articles of manufacture, and methods are disclosed. An example apparatus includes main memory, a memory hierarchy in circuit with the memory, buffer circuitry in circuit with the memory, and control circuitry to selectively couple programmable circuitry to the main memory via the cache circuitry or to the main memory via the buffer circuitry.