Memory Protection via Workset Address Translation
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Solution Overview
Problem
In conventional single-level store memory management techniques, protecting information across multiple processes is challenging as address spaces are managed using common logical addresses, leading to unintended visibility and potential destruction of data between processes, and existing methods require cumbersome data copying and address space switching to manage protection.
Innovation Solution
A semiconductor device and memory protection method that uses a single address system with worksets and page tables to manage virtual memory, allowing processes to reference information using logical addresses while switching page tables to control access, thereby preventing data destruction and enabling efficient data exchange without copying.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Device complexity
If single-level store memory management is used with common logical addresses, then address space management is simplified, but information protection between processes deteriorates
Solution Approach 1:
The patent segments the unified address space into multiple worksets, where each workset represents a separate logical address space for different processes. The address management unit maintains multiple workset information structures, each with its own address translation buffer, enabling process-specific address mapping while maintaining overall system simplicity.
Solution Approach 2:
The patent introduces an address management unit as an intermediary between the processor and memory device. This unit contains an address translation buffer that translates logical addresses to physical addresses while enforcing workset-specific access permissions, thereby protecting information between processes without requiring complex software-based memory management.
2Reliability
If data copying and address space switching are used for protection, then information protection is improved, but operation complexity and time loss worsen
Solution Approach 1:
The patent pre-establishes workset information structures and address translation buffers for each process before execution. Each workset has predetermined read/write/execute permissions configured in advance, eliminating the need for runtime data copying or address space switching during process execution.
Solution Approach 2:
The patent replaces the mechanical approach of data copying and address space switching with an electronic address translation mechanism. The address management unit performs on-the-fly address translation using the address translation buffer, substituting physical data movement with logical address manipulation, thereby improving operational efficiency.
3Reliability
If separate address spaces are maintained for each process, then information protection is improved, but address space management complexity worsens
Solution Approach 1:
The patent merges multiple separate address spaces into a unified address management structure. The address management unit maintains a single workset information structure that contains multiple workset entries, each representing a process's address space. This consolidation reduces management overhead while preserving process isolation through workset-specific permission bits.
4Reliability
If data copying is performed for protection, then information protection is improved, but productivity and time efficiency worsen
Solution Approach 1:
The patent eliminates the need for data copying by implementing virtual memory addressing with workset-specific address translation. Each process operates on its own logical address space, and the address management unit translates these to physical addresses without requiring actual data duplication, thereby maintaining productivity while ensuring protection.
Data Source
AI summary
According to one embodiment, a semiconductor device includes a processor, and a memory device. The memory device has a nonvolatile semiconductor storage device and is configured to serve as a main memory for the processor. When the processor executes a plurality of programs, the processor manages pieces of information required to execute the programs as worksets for the respective programs, and creates tables, which hold relationships between pieces of information required for the respective worksets and addresses of the pieces of information in the memory device, for the respective worksets. The processor accesses to the memory device with reference to the corresponding tables for the respective worksets.