WoW Semiconductor Die Package With High-k Layer for TSV Leakage
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Solution Overview
Problem
In wafer on wafer (WoW) semiconductor die packages, current leakage occurs due to trap-assist tunnels formed during the etching of TSV structures, leading to reduced performance and potential device failure, especially as device density increases.
Innovation Solution
A high dielectric constant (high-k) dielectric layer with intrinsic negative charge polarity is introduced over the device region, attracting hole charge carriers and suppressing trap-assist tunnels, thereby reducing current leakage and enabling closer placement of semiconductor devices.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If TSV structures are etched to increase device density, then device density increases, but current leakage increases due to trap-assist tunnels
Solution Approach 1:
A dielectric layer is introduced as an intermediary between the TSV structure and the semiconductor device. This dielectric layer acts as a mediator that blocks trap-assist tunnels formed during TSV etching, preventing current leakage while allowing the TSV structure to remain for electrical connectivity. The dielectric layer specifically targets and blocks the harmful trap-assist tunneling effect without interfering with the beneficial electrical connection function of the TSV.
Solution Approach 2:
The invention converts the harmful effect of trap-assist tunnels (current leakage) into a beneficial situation by using the etched TSV structure itself as part of the solution. The TSV etching process that creates trap-assist tunnels is also what enables close spacing of devices; by adding the dielectric layer, the harmful current leakage is blocked while the beneficial close spacing and electrical connectivity are preserved.
2Length of moving object
If TSV structures are etched closer together to reduce pitch, then device pitch decreases, but trap-assist tunnels form causing current leakage
Solution Approach 1:
The dielectric layer serves as a protective intermediary positioned between closely-spaced TSV structures. It mediates the interaction between adjacent TSVs by blocking the formation of trap-assist tunnels that would otherwise occur when TSVs are etched in close proximity, enabling reduced pitch without the harmful side effect of current leakage.
Solution Approach 2:
The dielectric layer is applied locally at specific regions where TSV structures are etched, particularly in areas where trap-assist tunnels are most likely to form. This localized application provides targeted protection against current leakage at the critical interfaces between TSV structures and semiconductor devices, while maintaining the overall close-pitch layout.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The high-k dielectric layer effectively reduces current leakage, enhances semiconductor device performance, and allows for increased device density by suppressing trap-assist tunnels, enabling reduced pitch and higher density in WoW semiconductor die packages.
Implementation Method 1
A high dielectric constant (high-k) dielectric layer with intrinsic negative charge polarity is introduced over the device region, attracting hole charge carriers and suppressing trap-assist tunnels
Implementation Method 2
A high dielectric constant (high-k) dielectric layer with intrinsic negative charge polarity is introduced over the device region
Data Source
AI summary
A semiconductor die package includes a high dielectric constant (high-k) dielectric layer over a device region of a first semiconductor die that is bonded with a second semiconductor die in a wafer on wafer (WoW) configuration. A through silicon via (TSV) structure may be formed through the device region. The high-k dielectric layer has an intrinsic negative charge polarity that provides a coupling voltage to modify the electric potential in the device region. In particular, the electron carriers in high-k dielectric layer attracts hole charge carriers in device region, which suppresses trap-assist tunnels that result from surface defects formed during etching of the recess for the TSV structure. Accordingly, the high-k dielectric layer described herein reduces the likelihood of (and/or the magnitude of) current leakage in semiconductor devices that are included in the device region of the first semiconductor die.