Wafer-on-Wafer Memory System with Differential Signal Transmission
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Solution Overview
Problem
Conventional memory systems face throughput bottlenecks due to limitations in wiring quantity and length, leading to increased power consumption and reduced performance, particularly in high-demand applications like blockchain servers.
Innovation Solution
The implementation of a wafer-on-wafer stacking architecture that uses differential signal technology to transmit data, combined with an integrated memory controller that eliminates the need for a physical layer controller, allowing for high-speed data transmission with low error rates and reduced power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Speed
If conventional single-ended signal transmission is used, then the system structure is simple, but the transmission speed is low and power consumption is high
Solution Approach 1:
The patent changes the signal transmission parameter from single-ended to differential mode. The signal interface converts single-ended signals from the logic circuit layer into differential signals for transmission through bounding pads to the memory crystal layer, achieving higher transmission speeds and lower power consumption while maintaining structural feasibility
2Productivity
If wiring quantity and length are increased to improve throughput, then data transmission capacity increases, but power consumption increases and performance degrades
Solution Approach 1:
The patent transitions from planar wiring to three-dimensional wafer-on-wafer stacking architecture. Multiple wafers are stacked vertically with bounding pads providing inter-layer connections, effectively increasing throughput capacity while reducing the horizontal wiring length and associated power consumption
3Ease of manufacture
If conventional memory controllers with separate physical layer controllers are used, then signal control is precise, but implementation cost is high
Solution Approach 1:
The patent merges the memory controller and physical layer controller functions into a single integrated controller. This integrated controller handles both memory management commands and physical layer signal conversion, eliminating the need for separate physical layer controllers and reducing implementation cost while maintaining signal control capability
Data Source
AI summary
A computer system configured to overcome the conventional bottleneck of memory throughput. A wafer-on-wafer (WOW) technology is adapted to overcome the physical limitation of quantity and length in circuit deployments. The memory devices and the memory controllers in the logic circuit layer are improved to transmit data in differential signals. The differential signals can significantly reduce the error rate in high-speed transmissions, at a voltage level far lower than that of the conventional single-end signals. Thus, the power consumption of the computer system is significantly reduced. Furthermore, the memory controller in the computer system is improved to be an integrated controller having control over physical layer signals. Thereby, the conventional physical layer interface is no longer needed in the computer system, and therefore the cost to the computer system is further reduced.