Wafer-on-Wafer Memory Die Stacking With Hybrid Bonding
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Solution Overview
Problem
Existing semiconductor packaging techniques face challenges such as reduced thermal conductivity, increased thermal dissipation, limited device density, and bandwidth due to the use of micro bumps and pick-and-place operations, which also limit throughput and increase power consumption.
Innovation Solution
The use of hybrid bonding and wafer on wafer (WoW) operations to join dies in stacks, combined with wafer thinning and interposers, enhances thermal performance, increases device density, and improves bandwidth by reducing electrical connection pitch and eliminating gaps between dies.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Temperature
If micro bumps and pick-and-place operations are used to connect dies, then electrical connections are established, but thermal conductivity is reduced and thermal dissipation increases
Solution Approach 1:
The patent merges the electrical connection function and thermal conduction function into a single integrated structure. By using hybrid bonding to directly connect dies without micro bumps, the electrical interconnects serve dual purposes: electrical signal transmission and thermal conduction path, thereby improving thermal conductivity while reducing thermal dissipation.
Solution Approach 2:
The patent extracts and eliminates the micro bump structure from the die connection process. By removing micro bumps and using direct hybrid bonding, the harmful thermal interruption caused by micro bump interfaces is eliminated, creating a continuous thermal path between dies while still establishing electrical connections.
2Quantity of substance
If micro bumps are used to connect dies, then electrical connections are established, but device density is limited
Solution Approach 1:
The patent changes the physical parameters of the connection structure by transitioning from micro bump-based connections to direct hybrid bonding. This parameter change enables significantly smaller connection pitches, allowing dies to be placed closer together and increasing the number of dies that can be integrated in a given area, thereby improving device density.
3Productivity
If pick-and-place operations are used to assemble dies, then dies can be positioned on substrates, but throughput is limited and power consumption increases
Solution Approach 1:
The patent applies preliminary action by performing die stacking and bonding operations while dies are still in wafer form, before individual die separation. This wafer-level processing allows multiple dies to be bonded simultaneously in a single operation, dramatically increasing throughput and reducing the energy consumption associated with repeated pick-and-place operations for each individual die.
Solution Approach 2:
The patent merges multiple individual die assembly operations into a single wafer-level bonding operation. By bonding entire wafers together in one step rather than placing individual dies sequentially, the process achieves higher throughput and lower power consumption per die assembled.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach improves thermal conductivity, reduces thermal dissipation, increases device density, and enhances bandwidth while reducing fabrication costs and improving throughput by eliminating pick-and-place operations and using tested dies.
Implementation Method 1
The use of hybrid bonding and wafer on wafer (WoW) operations to join dies in stacks
Implementation Method 2
combined with wafer thinning and interposers
Data Source
Figure 1A
Figure 1B
Figure 2A~2E
AI summary
A method may include positioning a first wafer on a second wafer, wherein the first wafer may include a first memory die and the second wafer may include a second memory die, bonding the first memory die and the second memory die to form a memory die stack, and positioning the memory die stack on an interface die. A device may include a first memory device stack comprising a first memory device bonded to a second memory device, a second memory device stack comprising a third memory device bonded to a fourth memory device, and an interface die attached to the first memory device stack and the second memory device stack. A method may include bonding a first memory die to a second memory die, modifying a thickness of the second memory die to form a modified memory die, and bonding a third memory die to the modified memory die.