Wafer-on-Wafer Interconnection Using Direct Bonded Socket STI Vias
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Solution Overview
Problem
Conventional wafer-on-wafer (WOW) packaging techniques, such as face-to-face (F2F) bonding, face-to-back (F2B) bonding, and hybrid bonding, face challenges like high thermal constraints, performance degradation, and increased fabrication costs due to the need for post-bond anneal processes and additional bonding procedures.
Innovation Solution
A direct bonding technique is applied to bond the frontside surfaces of CMOS and memory array wafers using dielectric-dielectric bonds with low thermal constraints, enabling improved routing flexibility and power distribution, and incorporating a double pad scheme with socket dielectric regions for interconnects, while maintaining cost competitiveness with hybrid bond techniques.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional hybrid bonding techniques are used for WOW packaging, then metal-metal connections can be achieved for data and control signals, but high thermal constraints and performance degradation occur due to post-bond anneal processes
Solution Approach 1:
The patent extracts and eliminates the post-bond anneal process from the hybrid bonding technique, replacing it with a direct bonding approach that achieves metal-metal connections without requiring high-temperature annealing, thereby resolving the thermal constraints while maintaining bonding interface quality
Solution Approach 2:
The patent changes the bonding parameters by transitioning from conventional hybrid bonding with annealing to a modified direct bonding process that operates at lower temperatures, fundamentally altering the thermal regime of the bonding operation to avoid performance degradation
2Reliability
If face-to-back bonding or additional bonding procedures are employed, then bonding can be achieved, but fabrication costs increase due to complex processing steps
Solution Approach 1:
The patent removes unnecessary additional bonding procedures and simplifies the process to a direct bonding approach, eliminating redundant steps that increase fabrication complexity and cost while maintaining effective bonding interface quality
Solution Approach 2:
Instead of following conventional multi-step bonding procedures, the patent inverts the approach by using a simplified direct bonding method that achieves the same or better results with fewer steps, thereby reducing manufacturing complexity and cost
3Reliability
If conventional WOW bonding processes are used, then wafers can be bonded, but routing flexibility and power distribution are limited
Solution Approach 1:
The patent segments the bonding interface design by incorporating socket dielectric regions and double pad schemes that allow independent routing paths and power distribution networks, enabling greater flexibility in metal routing layer design while maintaining bonding process stability
Solution Approach 2:
The patent adds dimensional complexity to the bonding interface by implementing multi-layer metal routing and socket dielectric structures that provide additional routing dimensions and paths, thereby enhancing flexibility without compromising the fundamental bonding stability
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach simplifies the WOW bonding process, reduces thermal stress, enhances interconnect alignment, and lowers fabrication costs, while maintaining high-quality bonding interfaces and flexibility in metal routing layer design, thus improving overall semiconductor device performance and manufacturing efficiency.
Implementation Method 1
bonding a frontside surface of the CMOS wafer to a frontside surface of the memory array wafer through direct bonding to form dielectric-dielectric bonds at the bonding interface
Data Source
AI summary
A semiconductor device assembly including a first module having one or more memory arrays, each of the one or more memory arrays being connected to a plurality of landing pads of the first module; and a second module having complementary metal-oxide-semiconductor devices, the second module including a plurality of socket shallow trench isolation (STI) regions disposed in a substrate of the second module, a plurality of metal routing layers connected to corresponding CMOS devices, a plurality of a first type of via contacts each being connected to a corresponding one of the plurality of metal routing layers, and a plurality of a second type of via contacts each being connected to a corresponding one of the plurality of landing pads of the first module, wherein the plurality of the first type of via contacts and the plurality of the second via contacts pass through the plurality of socket STI regions.