Wrap-Around Extrinsic Base HBT for Lower Rb and Ccb
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Solution Overview
Problem
Current integration schemes for heterojunction bipolar transistors (HBTs) result in high collector-base capacitance (Ccb) and high base resistance (Rb), which limit device scaling and performance in terms of cut-off frequencies (fT/fMAX) and breakdown voltage (BVceo).
Innovation Solution
A heterojunction bipolar transistor with a wrap-around extrinsic base and an inverted 'T' shaped spacer is designed, featuring a polysilicon emitter and an epitaxially grown SiGe intrinsic base, where the extrinsic base wraps around the emitter and intrinsic base, allowing for increased silicide and ohmic contact formation, thereby reducing Rb and enhancing fMAX.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional integration schemes are used for HBT fabrication, then manufacturing process is simple, but collector-base capacitance (Ccb) is high and base resistance (Rb) is high
Solution Approach 1:
The extrinsic base is extended into a wrap-around configuration that wraps around the emitter region, transitioning from a planar two-dimensional layout to a three-dimensional structure. This dimensional change increases the contact surface area between the extrinsic base and emitter, thereby reducing base resistance (Rb) and collector-base capacitance (Ccb) without significantly complicating the manufacturing process
Solution Approach 2:
The base region is divided into two distinct parts: an intrinsic base and an extrinsic base. The extrinsic base is further segmented to wrap around the emitter, creating multiple contact points. This segmentation allows independent optimization of the extrinsic base geometry to minimize parasitic effects while maintaining a relatively simple overall fabrication process
2Speed
If device scaling is performed to improve cut-off frequencies, then fT/fMAX increases, but base resistance (Rb) and collector-base capacitance (Ccb) increase
Solution Approach 1:
By wrapping the extrinsic base around the emitter in three dimensions, the contact perimeter is increased without proportionally increasing the planar footprint. This allows device scaling for higher cut-off frequencies while maintaining low base resistance (Rb) and collector-base capacitance (Ccb) through the enhanced contact surface area in the vertical dimension
Solution Approach 2:
The extrinsic base is configured to wrap around and partially overlap the emitter region, creating a nested configuration where the extrinsic base encompasses the emitter. This nesting increases the effective contact area between base and emitter, enabling device scaling to improve cut-off frequencies while keeping parasitic resistance and capacitance low
Data Source
AI summary
The present disclosure relates to semiconductor structures and, more particularly, to transistor with wrap-around extrinsic base and methods of manufacture. The structure includes: a substrate; a collector region within the substrate; an emitter region over the substrate and which comprises silicon based material; an intrinsic base; and an extrinsic base overlapping the emitter region and the intrinsic base; an extrinsic base overlapping the emitter region and the intrinsic base; and an inverted âTâ shaped spacer which separates the emitter region from the extrinsic base and the collector region from the emitter region.