Wrap-Around Control Gate MTP Memory for Coupling Ratio
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Solution Overview
Problem
Existing MTP memory devices face challenges with slow access time, smaller coupling ratio, and large cell size, which affect their performance in applications requiring customization and efficient data storage.
Innovation Solution
A novel MTP memory device with a wrap-around control gate is developed, featuring a semiconductor substrate with active and inactive regions, isolation material, and a floating gate cell, where the control gate wraps around the floating gate, improving capacitive coupling and reducing cell size.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional control gate configuration is used in MTP memory devices, then the device structure is simpler, but the coupling ratio is smaller and access time is slower
Solution Approach 1:
The control gate is extended from a conventional planar configuration into the trench to wrap around the floating gate, transitioning from a two-dimensional top surface arrangement to a three-dimensional structure that encompasses the floating gate on multiple sides, thereby enhancing capacitive coupling without significantly increasing overall device footprint
Solution Approach 2:
The control gate is positioned to wrap around and enclose portions of the floating gate, creating a nested configuration where the control gate structure contains the floating gate within its capacitive field, maximizing the coupling ratio by ensuring the control gate is in close proximity to the floating gate on multiple surfaces
2Speed
If a conventional control gate configuration is used, then the fabrication process is simpler, but the access time is slower
Solution Approach 1:
The control gate extends vertically into the trench and wraps around the floating gate, creating a three-dimensional capacitive coupling structure that enhances the electric field interaction between gates, thereby improving access time through stronger coupling without requiring complex multi-layer stacking
Solution Approach 2:
The control gate is positioned to provide enhanced capacitive coupling specifically at the interface with the floating gate in the trench region, while the rest of the device structure maintains conventional simplicity, allowing localized performance enhancement without global complexity increase
3Area of moving object
If existing MTP memory structures are used, then the cell design is conventional, but the cell size is large
Solution Approach 1:
The control gate wraps around the floating gate in the vertical dimension within the trench, utilizing three-dimensional space to achieve enhanced coupling ratio without increasing the lateral footprint of the memory cell, thereby improving coupling efficiency while maintaining compact cell size
Solution Approach 2:
The control gate and floating gate are merged into a single trench structure with the control gate wrapping around the floating gate, consolidating the capacitive coupling elements into a compact integrated structure that reduces overall cell area while enhancing coupling ratio
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The wrap-around control gate configuration enhances capacitive coupling between the control gate and floating gate, resulting in improved access times and a higher coupling ratio, addressing the limitations of existing MTP memory devices.
Implementation Method 1
the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate
Data Source
AI summary
One illustrative MPT device disclosed herein includes an active region and an inactive region, isolation material positioned between the active region and the inactive region, the isolation material electrically isolating the active region from the inactive region, and an FG MTP cell formed in the active region. In this example, the FG MTP cell includes a floating gate, wherein first, second and third portions of the floating gate are positioned above the active region, the inactive region and the isolation material, respectively, and a control gate positioned above at least a portion of the inactive region, wherein the control gate is positioned above an upper surface and adjacent opposing sidewall surfaces of at least a part of the second portion of the floating gate.