Wrap-around Fin for DRAM Capacitor Strap Contact
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Solution Overview
Problem
As semiconductor devices scale, providing a robust low resistance path for electrical conduction between an inner electrode of a transistor and the source of an access transistor becomes challenging due to the decreasing available area for forming a conductive strap structure, which affects the read and write times of a DRAM cell.
Innovation Solution
A conductive strap structure is formed in lateral contact with the inner electrode of a deep trench capacitor, and a semiconductor fin is created by patterning a spacer around this structure, allowing for the formation of a finFET access transistor with parallel channel regions.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If the available area for forming a conductive strap structure decreases due to device scaling, then the device density increases, but the resistance of the conductive path between the capacitor and access transistor increases
Solution Approach 1:
The conductive strap structure is formed extending in multiple dimensions around the capacitor, utilizing vertical and lateral space to create a low-resistance path without increasing the planar footprint. This multi-dimensional approach allows the conductive path to achieve lower resistance while maintaining high device density.
Solution Approach 2:
The conductive strap structure is nested around the capacitor, with the strap wrapping or surrounding the capacitor structure. This nesting arrangement allows the conductive path to be integrated within the existing capacitor geometry, reducing resistance without consuming additional area.
2Productivity
If the conductive strap structure area is reduced to maintain high device density, then the device scaling is achieved, but the read time and write time of the DRAM cell increase
Solution Approach 1:
The conductive strap structure is designed with varying cross-sectional areas and material compositions along its length, with thicker or more conductive sections positioned where current density is highest. This local optimization reduces resistance in critical regions without increasing the overall area, maintaining fast read/write times while achieving device scaling.
3Loss of time
If a low resistance conductive path is formed by increasing the conductive strap structure area, then the read time and write time are reduced, but the available device area decreases
Solution Approach 1:
The conductive strap structure employs dynamic geometry, changing cross-sectional dimensions at different locations along its path. The strap is wider and thicker in regions requiring lower resistance (near the access transistor and capacitor contacts) and narrower in less critical regions, optimizing the balance between resistance and area utilization.
Data Source
AI summary
A conductive strap structure in lateral contact with a top semiconductor layer is formed on an inner electrode of a deep trench capacitor. A cavity overlying the conductive strap structure is filled a dielectric material to form a dielectric capacitor cap having a top surface that is coplanar with a topmost surface of an upper pad layer. A semiconductor mandrel in lateral contact with the dielectric capacitor cap is formed. The combination of the dielectric capacitor cap and the semiconductor mandrel is employed as a protruding structure around which a fin-defining spacer is formed. The semiconductor mandrel is removed, and the fin-defining spacer is employed as an etch mask in an etch process that etches a lower pad layer and the top semiconductor layer to form a semiconductor fin that laterally wraps around the conductive strap structure. An access finFET is formed employing two parallel portions of the semiconductor fin.