Wrap Around Gate FET Uniform Channel Modulation

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Solution Overview

Problem

Existing field-effect transistors (FETs) with castellation structures lack uniform modulation of channel layers, leading to suboptimal current amplification due to limited electrical contact and field application, particularly on the sides of the castellation structures.

Innovation Solution

A wrap-around gate FET (WAGFET) design featuring heavily doped gate layers and castellation structures with gate metal deposited on and between the structures for direct electrical contact, allowing modulation from all directions, including the sides and top of the channel layers.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Manufacturing precision

If a common gate metal is deposited on the base structure to enclose castellation structures, then the electric field can modulate the channel layer, but the modulation is not uniform particularly on the sides of the castellation structures

Engineering Contradiction:

Improveuniformity of channel layer modulationVSAvoidelectrical contact quality

Core Design Contradiction:

Manufacturing precisionVSEase of operation

Solution Approach 1:

The gate structure is segmented into multiple independent gate electrodes positioned at different locations (top, sides, and bottom of channel layers) rather than a single common gate metal. This segmentation allows each gate electrode to independently modulate its respective channel layer region, achieving uniform modulation across all sides of the castellation structures.

Inventive Principle:

Principle #1Segmentation

Solution Approach 2:

The gate configuration transitions from a two-dimensional planar gate metal deposition to a three-dimensional wrap-around gate structure that contacts the channel layer from multiple spatial dimensions (top, sides, and bottom). This dimensional expansion enables comprehensive electrical contact and uniform electric field distribution around the castellation structures.

Inventive Principle:

Principle #17Another dimension (Dimensionality change)

2Ease of manufacture

If gate metal is deposited only on the base structure, then the structure is simple to manufacture, but electrical contact with channel layers is limited

Engineering Contradiction:

Improvegate metal deposition processVSAvoidelectrical contact reliability

Core Design Contradiction:

Ease of manufactureVSReliability

Solution Approach 1:

The gate electrodes are nested within and around the castellation structures, with gate electrodes positioned inside recesses and on surfaces of the castellation structures. This nested configuration maximizes electrical contact area and reliability while maintaining a compact manufacturing process that builds upon the existing castellation structure geometry.

Inventive Principle:

Principle #7Nested doll (Nesting)

3Power

If the gate structure encloses all castellation structures, then current amplification is improved, but the electric field distribution becomes non-uniform

Engineering Contradiction:

Improvecurrent amplificationVSAvoidelectric field distribution uniformity

Core Design Contradiction:

PowerVSManufacturing precision

Solution Approach 1:

Different gate electrodes are positioned to provide localized electric fields to specific regions of the channel layers (top surfaces, side surfaces, and bottom surfaces). Each gate electrode is optimized for its local region, ensuring uniform electric field distribution and consistent current amplification across all channel layer locations rather than relying on a single enclosing gate structure.

Inventive Principle:

Principle #3Local quality

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

This design enhances current amplification by providing uniform modulation, improving linearity and signal strength through uniform population of channel layers, resulting in improved performance.

Implementation Method 1

An electric signal applied to the gate terminal creates an electrical field that modulates the carriers in the channel layer

Methodology Applied

Scientific EffectElectric Field: Electric Field

Implementation Method 2

gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer

Methodology Applied

Scientific EffectElectrical Conduction: Conduction (electrical)

Data Source

PatentUS9882000B2Wrap around gate field effect transistor (WAGFET)

Publication Date: 2018.01.30 NORTHROP GRUMMAN SYSTEMS CORP

AI summary

A field effect transistor (FET) including a substrate, a plurality of semiconductor epitaxial layers deposited on the substrate, and a heavily doped gate layer deposited on the semiconductor layers. The FET also includes a plurality of castellation structures formed on the heavily doped gate layer and being spaced apart from each other, where each castellation structure includes at least one channel layer. A gate metal is deposited on the castellation structures and between the castellation structures to be in direct electrical contact with the heavily doped gate layer. A voltage potential applied to the gate metal structure modulates the at least one channel layer in each castellation structure from an upper, lower and side direction.