Wrap-Around OTP Memory Circuit for Smaller Bitcells
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Solution Overview
Problem
Conventional OTP memory circuits face challenges with large bitcell size and inefficient programming, which affect device performance and efficiency.
Innovation Solution
A polysilicon wrap-around memory circuit is designed with a recessed shallow trench isolation structure and a gate structure that overlaps with diffusion regions, featuring a wrap-around semiconductor corner, enhancing compactness and read current efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If conventional OTP memory circuits are used, then the memory function is achieved, but the bitcell size becomes large and programming efficiency is poor
Solution Approach 1:
The gate structure extends into the recessed STI region, utilizing the vertical dimension beneath the STI to accommodate additional gate length. This dimensional transition allows the transistor to achieve longer channel length for improved programming efficiency without increasing the planar footprint of the bitcell, effectively resolving the contradiction between programming efficiency and bitcell area.
2Power
If the gate structure is extended to improve read current, then read current increases, but the device complexity increases
Solution Approach 1:
The gate structure is merged with the recessed STI region, where the gate extends into the recess to directly overlap with the active region. This merging allows the gate to achieve longer effective length for higher read current while utilizing the existing STI recess space, thereby avoiding additional structural complexity that would arise from separate components.
Data Source
AI summary
The present disclosure relates to a structure which includes a semiconductor substrate, a recessed shallow trench isolation structure within the semiconductor substrate, and a gate structure provided at least partially over the recessed shallow isolation structure.