Wrap-Around Contacts in Zero Diffusion Break Layouts
Find Innovative SolutionsGenerate Solutions
Solution Overview
Problem
The scaling of multi-gate transistors to sub-10 nanometer nodes is limited by variability in conventional fabrication processes, leading to challenges in contact resistance and layout constraints, particularly with zero diffusion break structures.
Innovation Solution
The implementation of zero diffusion break with wrap-around contacts and backside power delivery, along with differentiated backside access features, to reduce contact resistance and improve layout efficiency.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If conventional fabrication processes are used for multi-gate transistor scaling, then existing infrastructure compatibility is maintained, but manufacturing precision deteriorates at sub-10 nanometer nodes due to process variability
Solution Approach 1:
The patent segments the contact structure into multiple components: shallow trench isolation regions, wrap-around contacts extending under the gate, and differentiated backside access features. This segmentation allows each component to be optimized independently for sub-10nm precision while maintaining compatibility with existing fabrication infrastructure.
Solution Approach 2:
The patent introduces wrap-around contacts that extend laterally under the gate electrode and differentiated backside access features that utilize the vertical dimension. This dimensional approach enables precise control of contact resistance and layout optimization without compromising planar fabrication process reliability.
2Productivity
If zero diffusion break structure is implemented, then transistor count per area increases, but contact resistance increases due to layout constraints
Solution Approach 1:
The wrap-around contacts extend laterally under the gate electrode into the isolation region, utilizing the lateral dimension to reduce contact resistance without increasing the planar footprint. This enables zero diffusion break structures to achieve high transistor density while maintaining low contact resistance through three-dimensional contact paths.
Solution Approach 2:
The wrap-around contacts are nested within the isolation region and extend under the gate, effectively utilizing the space that would otherwise be wasted. This nesting approach allows contact structures to be embedded within the device layout, reducing parasitic resistance without consuming additional area.
3Productivity
If device area is reduced to increase density, then transistor count per area improves, but power delivery capability deteriorates
Solution Approach 1:
The differentiated backside access features utilize the vertical dimension by creating deeper contact trenches and extending contact structures to the backside of the substrate. This three-dimensional approach enables efficient power delivery through vertical interconnects, allowing reduced planar device area while maintaining adequate power supply capability through the added vertical dimension.
Solution Approach 2:
The power delivery network is segmented into separate frontside and backside access features, allowing independent optimization of signal and power paths. This segmentation enables compact device layouts with dedicated vertical power vias that do not compete for planar space with transistor channels.
Data Source
AI summary
Integrated circuit structures having zero diffusion break and wrap-around contacts are described. In an example, an integrated circuit structure includes first and second pluralities of horizontally stacked nanowires or fins, and first and second gate stacks. An epitaxial source or drain structure is between the first plurality of horizontally stacked nanowires or fin and the second plurality of horizontally stacked nanowires or fin, the epitaxial source or drain structure having a cut extending there through to separate a first portion of the epitaxial source or drain structure from a second portion of the epitaxial source or drain structure.