Wrap Gate Vertical Select Transistors for ReRAM
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Solution Overview
Problem
Conventional vertical select field effect transistors in ReRAM devices have suboptimum on current and contact RC due to the configuration of the select gate electrode, leading to non-uniform and unreliable switching characteristics.
Innovation Solution
The use of a wrap-around select gate electrode that surrounds the entire channel region of the transistor, improving on current and reducing contact RC between the select gate electrode and the semiconductor pillars.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional vertical select field effect transistor configuration is used, then the device structure is simpler, but the on current is suboptimum and contact RC is high leading to non-uniform switching characteristics
Solution Approach 1:
The gate electrode is configured to wrap around the channel region in three dimensions, transitioning from a planar two-dimensional gate structure to a three-dimensional wrap-around structure. This dimensional change allows the gate to contact the channel from multiple directions, improving control over the channel and reducing contact resistance while maintaining manufacturing feasibility through sequential deposition and patterning steps
2Reliability
If the select gate electrode does not surround the channel region, then the manufacturing process is simpler, but the on current is insufficient and switching characteristics are non-uniform
Solution Approach 1:
The gate electrode formation process is segmented into multiple discrete steps: first forming a gate dielectric layer conformally on the channel region, then depositing a conductive material layer, and finally patterning to create the wrap-around structure. This segmentation of the manufacturing process makes the complex three-dimensional gate structure achievable through standard semiconductor fabrication techniques, reducing overall manufacturing difficulty
3Power
If a wrap-around select gate electrode is used, then on current is improved and contact RC is reduced, but the gate electrode configuration becomes more complex
Solution Approach 1:
The wrap-around gate electrode structure merges the gate function with the channel sidewalls, creating a unified structure where the gate dielectric and conductive material are deposited conformally to follow the channel geometry. This merging eliminates the need for separate gate alignment and contact structures, improving on current through better electrical contact while the conformal deposition process keeps the manufacturing complexity manageable
Data Source
AI summary
A gate dielectric layer and a gate electrode layer are formed around semiconductor pillars. The gate electrode layer is patterned to remove top portions that protrude above the semiconductor pillars and divided into multiple strips. Each strip constitutes a gate electrode line including a horizontal layer portion and a plurality of surrounding portions that entirely laterally surround respective channel regions of the semiconductor pillars to form wrap gate vertical select field effect transistors. Vertical stacks of memory elements and alternating layer stacks including a vertically alternating sequence of insulating strips and electrically conductive word line strips are formed above the vertical field effect transistors. Vertical bit lines can be formed inside the vertical stacks of memory elements.