Wrap-Around Read Register Control for Low-Power Flash Memory
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Solution Overview
Problem
Conventional flash memory devices experience high power consumption during wrap around read operations due to continuous operation of the word line and sensing amplifier, which is inefficient.
Innovation Solution
Implement a memory device with a control signal to disable the word line decoder, bit line decoder, and sensing amplifier circuit after the first read operation, utilizing a register circuit to output successive data, thereby reducing power consumption.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If the word line decoder, bit line decoder, and sensing amplifier circuit remain conductive and operational during wrap around read operation, then data reading can continue smoothly, but the power consumption of the flash memory becomes quite high
Solution Approach 1:
The patent applies dynamics by transitioning the word line decoder, bit line decoder, and sensing amplifier circuit from a continuous operational state to a dynamic state where they are disabled after the first read operation. The register circuit takes over the data output function, allowing the system to adapt its operational components based on the read operation phase, thereby reducing power consumption while maintaining data reading capability.
Solution Approach 2:
The patent extracts the data storage and output function from the word line decoder, bit line decoder, and sensing amplifier circuit by introducing a register circuit. The register circuit latches the first wrap around read data and outputs successive wrap around read data without requiring the continuous operation of the decoder and amplifier circuits, effectively separating the data retrieval function from the data output function.
2Use of energy by moving object
If the word line decoder, bit line decoder, and sensing amplifier circuit are disabled after the first read operation, then power consumption is reduced, but the complexity of controlling when to disable and enable components increases
Solution Approach 1:
The register circuit performs self-service by automatically latching the first wrap around read data and generating control signals to disable the word line decoder, bit line decoder, and sensing amplifier circuit after the first read operation. The register circuit uses its own operational state to control the disabling of other components, eliminating the need for external control logic and simplifying the overall system control.
Solution Approach 2:
The register circuit is configured to prepare and latch the first wrap around read data in advance, then use this latched data to generate control signals that disable the word line decoder, bit line decoder, and sensing amplifier circuit before subsequent read operations are needed. This preliminary preparation allows for efficient power management without increasing control complexity.
Data Source
AI summary
A memory device including a memory cell array, a signal generator, a word line decoder, a bit line decoder, a sensing amplifier circuit and a register circuit is provided. The signal generator generates a control signal according to a wrap around read command. The word line decoder, the bit line decoder, and the sensing amplifier circuit read data stored in the memory cell array according to the wrap around read command, so as to output a first wrap around read data. The register circuit is configured to latch the first wrap around read data and outputs successive wrap around read data according to the control signal and the latched first wrap around read data after the first wrap around read data is output. When the register circuit outputs the successive wrap around read data, the word line decoder, the bit line decoder, and the sensing amplifier circuit are disable.