Wrap-Around Backside Contact Layout for Low-RC Semiconductor Interconnects
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Solution Overview
Problem
Current semiconductor processing methods face challenges in forming backside contacts due to high resistance-capacitance products, especially when high-temperature annealing is not feasible during BEOL interconnect formation on the frontside of semiconductor substrates.
Innovation Solution
The formation of a fully wrapped-around backside contact is achieved by creating source/drain regions within the backside contact, utilizing a series of intermediate fabrication stages that include etching, deposition, and removal of sacrificial layers, followed by the formation of backside BEOL interconnects, which reduces resistance-capacitance issues.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional backside contact formation methods are used, then manufacturing simplicity is maintained, but resistance-capacitance products remain high
Solution Approach 1:
The backside contact formation is divided into multiple discrete stages: forming sacrificial layers, creating openings, depositing contact materials, and removing sacrificial layers. This segmentation allows each step to be optimized independently, achieving low resistance-capacitance products while maintaining manufacturing feasibility through systematic process breakdown.
Solution Approach 2:
Sacrificial layers are formed in advance before the actual contact formation. These preliminary structures guide subsequent processing steps and enable precise contact alignment. The sacrificial layers are removed after serving their guiding function, leaving clean contact openings with optimal electrical properties.
2Reliability
If high-temperature annealing is performed during BEOL interconnect formation, then electrical properties improve, but fabrication constraints increase
Solution Approach 1:
The contact structure parameters are optimized through controlled deposition thicknesses and geometric configurations rather than relying on high-temperature annealing. By adjusting contact opening dimensions, material layer thicknesses, and wrap-around geometry, optimal electrical properties are achieved at lower temperatures, maintaining fabrication flexibility.
3Reliability
If source/drain regions are fully disposed within backside contact, then resistance-capacitance products are minimized, but device complexity increases
Solution Approach 1:
The backside contact structure is designed to fully envelop the source and drain regions, merging the contact function with the interconnect structure. This wrap-around configuration creates a unified electrical pathway that minimizes resistance-capacitance products while the modular fabrication process keeps the increased structural complexity manageable.
Data Source
AI summary
A semiconductor structure includes a backside contact, and a source/drain region fully disposed within the backside contact.