Wrap-Around Back-Side Contacts for Dense Transistor Cells
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Solution Overview
Problem
Transistor cell density is limited by the challenges of scaling interconnects, particularly in achieving low resistance and power delivery, with back-side device contacts occupying significant cell area and causing resistance crowding and capacitance penalties.
Innovation Solution
The implementation of wrap-around metallization contacts that connect from the back-side to the front-side of transistor devices, minimizing cell area impact by using epitaxial source and drain semiconductors, such as SiGe, with direct metal connections that wrap around the source and drain semiconductors to interconnect front and back-side metal layers.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If back-side device contacts are employed to provide power interconnects, then power delivery capability is improved, but cell area is significantly occupied limiting area scaling
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional wrap-around contacts that extend vertically and wrap around the sides of transistor structures. This dimensional change allows power connections to be made without occupying additional cell area, as the contacts utilize the vertical dimension and side surfaces of existing structures.
Solution Approach 2:
The wrap-around contacts are nested within and around the transistor structure, following the contours of the source and drain regions. The contact structure is embedded within the cell area rather than adding external connections, effectively nesting the power delivery path within the existing device footprint.
2Productivity
If multiple nearby devices share a single power source, then cell density is improved, but resistance crowding effects occur causing voltage drops
Solution Approach 1:
The patent provides dedicated wrap-around contacts to individual transistor devices, segmenting the power delivery path so that each device has its own direct connection to the power source. This eliminates the shared power path that causes resistance crowding, as each device draws power through its own isolated contact structure.
3Productivity
If transistor area is decreased to increase cell density, then cell density is improved, but interconnect scaling becomes increasingly difficult
Solution Approach 1:
The wrap-around contacts are localized to specific regions around individual transistor devices, with each contact structure tailored to its local geometry. This localized approach simplifies interconnect scaling, as the contact formation process automatically adapts to the local device dimensions without requiring complex global interconnect routing.
Data Source
Figure 1A~1D
Figure 2
Figure 3A
AI summary
Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.