Wrap-Around Back-Side Source/Drain Contacts for Dense Transistor Cells
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Solution Overview
Problem
Transistor cell density is limited by the challenges of scaling interconnects, particularly in achieving low resistance and power delivery, with back-side device contacts occupying significant cell area and causing resistance crowding and voltage drops.
Innovation Solution
The implementation of wrap-around metallization contacts that extend from the top and side surfaces of source and drain semiconductors to the back-side metal, allowing for direct metal connections that minimize cell area impact and reduce contact resistance.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Power
If deep trench-like interconnects are employed to provide power from the back-side, then power delivery is achieved, but significant cell area is utilized which limits area scaling
Solution Approach 1:
The patent transitions from planar power delivery to three-dimensional wrap-around metallization that extends from the front surface, through the substrate, to the back surface. This vertical dimension utilization allows power connections without occupying additional lateral cell area, directly resolving the contradiction between power delivery capability and cell area consumption
2Productivity
If multiple nearby devices share a single power source, then device density increases, but resistance crowding effects occur causing voltage drops
Solution Approach 1:
The patent implements individual wrap-around power connections for each transistor device, segmenting the power delivery path rather than using shared power rails. This segmentation eliminates resistance crowding effects by providing dedicated low-resistance paths for each device, maintaining voltage stability while enabling high device density
3Productivity
If transistor area decreases to increase cell density, then more devices fit in the cell, but scaling interconnects becomes increasingly difficult
Solution Approach 1:
The wrap-around metallization structure utilizes the vertical dimension by extending through the substrate thickness, allowing power interconnects to bypass the lateral scaling constraints. This three-dimensional approach maintains effective power delivery even as transistor dimensions shrink and lateral interconnect space becomes limited
Data Source
AI summary
Back-side transistor contacts that wrap around a portion of source and/or drain semiconductor bodies, related transistor structures, integrated circuits, systems, and methods of fabrication are disclosed. Such back-side transistor contacts are coupled to a top and a side of the source and/or drain semiconductor and extend to back-side interconnects. Coupling to top and side surfaces of the source and/or drain semiconductor reduces contact resistance and extending the metallization along the side reduces transistor cell size for improve device density.