Nonvolatile Memory Transistor with Wraparound Control Gate
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Solution Overview
Problem
Existing nonvolatile semiconductor memory transistors face challenges in increasing the capacitance between the floating gate and the control gate, which hinders efficient writing and erasing of data, as the thickness of the floating gate affects the capacitive coupling.
Innovation Solution
A nonvolatile semiconductor memory transistor structure is developed using an island-shaped semiconductor with a floating gate surrounding the channel region and a control gate surrounding the floating gate, with an inter-polysilicon insulating film and a tunnel insulating film to enhance capacitance, along with a control gate line electrically connected to the control gate, and a thicker first insulating film below the floating gate.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If the thickness of the floating gate is increased to increase the capacitance between the floating gate and the control gate, then the capacitive coupling is improved, but the device structure becomes more complex and manufacturing difficulty increases
Solution Approach 1:
The patent applies nesting by placing the floating gate inside a cavity formed in the insulating film, with the control gate surrounding it. This nested configuration allows the control gate to wrap around the floating gate on multiple surfaces (top, bottom, and sidewalls), significantly increasing the capacitance between gates without requiring the floating gate itself to be thicker. The tunnel insulating film is also nested within this structure, positioned between the floating gate and the semiconductor substrate.
2Productivity
If the floating gate thickness is increased to improve capacitance, then writing and erasing efficiency is improved, but the manufacturing precision requirements increase
Solution Approach 1:
The patent transitions from a planar capacitance configuration to a three-dimensional wrapped configuration. Instead of relying solely on the top surface area of the floating gate (two-dimensional), the control gate extends to surround the floating gate on multiple surfaces including the bottom and sidewalls. This dimensional expansion increases the effective capacitance area without requiring increased floating gate thickness, thereby maintaining manufacturing precision while improving writing and erasing efficiency.
3Device complexity
If the control gate is designed to cover only the top surface of the floating gate, then the device structure is simpler, but the capacitance between floating gate and control gate is insufficient
Solution Approach 1:
The control gate is designed to nest around the floating gate in a wraparound configuration. The control gate is positioned such that it surrounds the floating gate on the top surface, bottom surface, and sidewalls, creating a nested structure where the control gate envelops the floating gate. This multi-surface coverage maximizes the capacitance between the two gates while maintaining a relatively simple overall device structure.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This configuration effectively increases the capacitance between the floating gate and the control gate, improving the efficiency of data writing and erasing processes.
Implementation Method 1
a tunnel insulating film is interposed between the floating gate and the channel region
Implementation Method 2
an inter-polysilicon insulating film is interposed between the control gate and the floating gate
Data Source
AI summary
A nonvolatile semiconductor memory transistor includes an island-shaped semiconductor having a source region, a channel region, and a drain region formed in this order from the silicon substrate side, a floating gate arranged so as to surround the outer periphery of the channel region with a tunnel insulating film interposed between the floating gate and the channel region, a control gate arranged so as to surround the outer periphery of the floating gate with an inter-polysilicon insulating film interposed between the control gate and the floating gate, and a control gate line electrically connected to the control gate and extending in a predetermined direction. The inter-polysilicon insulating film is interposed between the floating gate and the lower and inner side surfaces of the control gate and between the floating gate and the lower surface of the control gate line.