Wraparound Gate Semiconductor Structure for Uniform Electric Field
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Solution Overview
Problem
Existing semiconductor devices face challenges in achieving high breakdown voltage and improved gate control capability due to uneven electric field distribution, particularly at the edges of gate and drain electrodes.
Innovation Solution
A semiconductor structure is proposed, comprising a substrate with a channel structure, N-type heavily doped layers, and a gate electrode. The channel structure includes a first intermediate layer, a channel layer with a smaller cross-sectional width, and a second intermediate layer that covers the channel layer's sidewalls and surface. The gate electrode covers the sidewalls of the doped layers and channel structure, enhancing gate control and uniform electric field distribution.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a planar device structure is used, then the device is simple to manufacture, but the electric field distribution is uneven causing severe concentration at electrode edges
Solution Approach 1:
The patent transitions from a planar two-dimensional device structure to a three-dimensional structure where the gate electrode wraps around the channel structure. This dimensional change allows the gate to control the channel from multiple directions (top and sidewalls), achieving more uniform electric field distribution while maintaining manufacturing feasibility through sequential layer deposition processes
2Device complexity
If the gate electrode only covers the top surface, then the manufacturing process is simple, but the gate control capability is insufficient
Solution Approach 1:
The gate electrode structure is designed to wrap around the channel, with the gate encompassing the channel from the top and extending down the sidewalls. This nested configuration allows the gate to control the channel more effectively by surrounding it, improving gate control capability while the channel structure remains integrated within the gate's protective envelope
3Ease of manufacture
If the channel layer has the same width as intermediate layers, then the manufacturing process is simpler, but the gate control over the channel is weaker
Solution Approach 1:
The channel layer is designed with a narrower width compared to the intermediate layers, creating a localized constriction in the channel region. This local dimensional change enhances gate control by concentrating the electric field more effectively over the active channel area, while the wider intermediate layers provide sufficient material for gate electrode formation and structural support
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The semiconductor structure achieves improved gate control capability and significantly enhanced breakdown voltage, reducing leakage and improving dynamic characteristics and efficiency.
Implementation Method 1
The gate electrode is in ohmic contact with the first N-type heavily doped layer and the second N-type heavily doped layer
Implementation Method 2
Under a reverse bias, a distribution of electric field in a device is usually uneven. Generally, severe electric field concentration occurs at an edge of the gate electrode or the drain electrode
Data Source
AI summary
The present disclosure provides a semiconductor structure, including: a substrate; a channel structure on the substrate, a first N-type heavily doped layer and a second N-type heavily doped layer. The channel structure includes a first intermediate layer, a channel layer, and a second intermediate layer that are sequentially arranged on the substrate, where a width of a cross-section of the channel layer is smaller than a width of a cross-section of the first intermediate layer, and the second intermediate layer covers sidewalls of the channel layer and a surface of the channel layer far from the first intermediate layer. The first N-type heavily doped layer is between the substrate and the channel structure, and the second N-type heavily doped layer is on a side of the channel structure far from the substrate.