Wraparound Gate Structures Along Semiconductor Pillars for Stronger Coupling
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Solution Overview
Problem
Existing methods for fabricating transistors with conductive gates along pillars of semiconductor material face challenges in achieving strong coupling between the gates and channel regions, particularly as device dimensions shrink.
Innovation Solution
The method involves forming semiconductor material pillars within an array, initially alternating with insulative material, which is then recessed or removed, allowing conductive lines to wrap partially or entirely around the pillars, enhancing gate-channel coupling.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional transistor fabrication methods are used, then manufacturing simplicity is maintained, but gate-channel coupling strength is insufficient
Solution Approach 1:
The gate structure transitions from a planar configuration to a three-dimensional wraparound structure that envelops the channel pillar. This dimensional change allows the gate to contact the channel from multiple directions (top, sidewalls), dramatically improving gate-channel coupling strength without requiring fundamentally new fabrication approaches, as it builds upon existing conformal deposition and etch techniques.
Solution Approach 2:
The fabrication process is divided into distinct stages: forming the channel pillar, depositing gate material conformally around it, and selectively removing portions of the gate structure. This segmentation allows each step to be optimized independently while maintaining overall process feasibility with standard semiconductor manufacturing techniques.
2Productivity
If device dimensions are scaled down to increase integration density, then productivity is improved, but achieving strong gate-channel coupling becomes more difficult
Solution Approach 1:
As device dimensions shrink, the wraparound gate configuration becomes even more effective because the gate can approach the channel from multiple directions in three-dimensional space. This multi-directional coupling compensates for the reduced scale, maintaining strong electrical control over the channel despite smaller feature sizes and enabling continued scaling for higher integration density.
3Reliability
If conductive lines wrap entirely around pillars, then gate-channel coupling is maximized, but manufacturing complexity increases
Solution Approach 1:
The gate structure can be configured to wrap partially or entirely around the channel pillar depending on the specific application requirements. This flexibility allows designers to optimize for coupling strength when needed, or simplify the structure for easier manufacturing when coupling can be achieved through partial wrapping, providing a tunable solution that balances performance and fabrication ease.
Data Source
AI summary
Some embodiments include an assembly having pillars of semiconductor material arranged in rows extending along a first direction. The rows include spacing regions between the pillars. The rows are spaced from one another by gap regions. Two conductive structures are within each of the gap regions and are spaced apart from one another by a separating region. The separating region has a floor section with an undulating surface that extends across semiconductor segments and insulative segments. The semiconductor segments have upper surfaces which are above upper surfaces of the insulative segments; Transistors include channel regions within the pillars of semiconductor material, and include gates within the conductive structures. Some embodiments include methods for forming integrated circuitry.