Wrap-Around MOL Contact With Backside S/D Cut for Scaled Power Delivery
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Solution Overview
Problem
The challenge in semiconductor device fabrication is to optimize the performance of devices and interconnects as feature sizes shrink, particularly in forming reliable contacts and power delivery networks in tight spaces.
Innovation Solution
A semiconductor device fabrication method that includes executing front-end-of-line (FEOL) processing to form source/drain epitaxy, forming a middle-of-line (MOL) contact, executing a self-aligned backside source/drain cut, depositing metallic material, and forming silicide to enhance conductivity and contact reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If feature sizes are shrunk to increase device density, then capacity increases, but performance optimization becomes increasingly difficult
Solution Approach 1:
The patent forms silicide contacts on the sidewalls of source/drain epitaxy structures, transitioning from planar top-down contacts to three-dimensional wrap-around contacts. This dimensional change allows electrical contact to be established through the vertical sidewalls, enabling improved performance in scaled devices without increasing planar footprint.
Solution Approach 2:
The silicide contact structure is formed within and along the sidewalls of the source/drain epitaxy regions, creating a nested configuration where the conductive silicide path is embedded within the device structure. This nested arrangement provides reliable electrical connection while maintaining compact device geometry.
2Ease of manufacture
If conventional contact methods are used in scaled devices, then manufacturing simplicity is maintained, but contact reliability deteriorates
Solution Approach 1:
The silicide contact structure utilizes the source/drain epitaxy sidewalls themselves as the contact formation substrate. The epitaxy growth and subsequent silicide deposition automatically create the contact path without requiring separate contact hole formation or alignment steps, enabling self-aligned contact formation that is both simple to manufacture and highly reliable.
3Quantity of substance
If power delivery networks are implemented in scaled devices, then capacity increases, but interconnect performance optimization becomes increasingly significant
Solution Approach 1:
The patent implements localized silicide contact regions on the sidewalls of source/drain structures, creating high-conductivity pathways precisely where needed for power delivery. This local quality enhancement provides optimized electrical connection at critical interconnect points without requiring global redesign of the entire power delivery network.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The method achieves improved and more reliable conductivity by forming silicide contacts and gouged contacts, which enable efficient power delivery and interconnect performance even in scaled-down semiconductor devices.
Implementation Method 1
depositing metallic material along the respective sides of each of the first and second S/D epitaxy in the opening and forming silicide from the metallic material
Data Source
AI summary
A semiconductor device fabrication method is provided and includes executing front-end-of-line (FEOL) processing to form first and second source/drain (S/D) epitaxy, forming a middle-of-line (MOL) contact to the first S/D epitaxy, executing a self-aligned backside S/D cut to form an opening in which respective sides of each of the first and second S/D epitaxy are exposed, depositing metallic material along the respective sides of each of the first and second S/D epitaxy in the opening and forming silicide from the metallic material whereby the silicide at the first S/D epitaxy contacts the MOL contact and the sides of the first S/D epitaxy.