Wrap-Around Silicide Layer for Low-Resistance Source/Drain Contacts

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Solution Overview

Problem

As semiconductor devices continue to shrink in size, forming silicide layers between source/drain contacts and epitaxial source/drain features becomes challenging due to decreasing gate pitches, leading to difficulties in achieving satisfactory silicide formation.

Innovation Solution

A process is developed to form a wrap-around silicide layer that covers the top surface and sidewalls of source/drain features, involving the deposition of a first contact etch stop layer and interlayer dielectric, followed by selective etching and silicide deposition, with additional layers deposited over the silicide layer to enhance the process window and reduce contact resistance.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional silicide formation processes are used, then manufacturing simplicity is maintained, but contact resistance increases and process window decreases as gate pitch shrinks

Engineering Contradiction:
Improvecontact resistanceVSAvoidprocess complexity
Core Design Contradiction:
ReliabilityVSEase of manufacture

Solution Approach 1:

The silicide formation process is segmented into multiple sequential steps: forming first and second contact etch stop layers at different levels, selective etching to create access trenches, depositing silicide layer, and forming contact openings. This segmentation allows each step to be optimized independently, achieving low contact resistance through wrap-around silicide while maintaining manufacturability through standardized process modules

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The silicide layer is formed to wrap around the source/drain features in three dimensions, extending along sidewalls and wrapping over top surfaces. This dimensional approach increases the contact surface area between silicide and source/drain regions, reducing contact resistance without requiring proportional increases in gate pitch or device area

Inventive Principle:
Principle #17Another dimension (Dimensionality change)

2Productivity

If gate pitch is reduced to increase device density, then productivity increases, but silicide formation becomes more difficult

Engineering Contradiction:
Improvedevice densityVSAvoidsilicide formation difficulty
Core Design Contradiction:
ProductivityVSEase of manufacture

Solution Approach 1:

Contact etch stop layers are formed preliminarily before silicide deposition, with the first CESL extending along sidewalls and the second CESL wrapping over top surfaces. This preliminary structuring creates defined access trenches that guide subsequent silicide formation, enabling reliable silicide deposition even at reduced gate pitches where conventional approaches fail

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The contact etch stop layers serve as intermediary structures that mediate between the source/drain features and the silicide layer. These intermediary layers provide a controlled interface that facilitates uniform silicide deposition and defines the wrap-around geometry, making the process robust against variations in gate pitch

Inventive Principle:
Principle #24Intermediary (Mediator)

Applied Scientific Principles

This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.

Function Achieved in This Case

The wrap-around silicide layer provides an improved process window and reduces contact resistance by increasing the contact surface area, addressing the challenges of shrinking gate pitches and enhancing the manufacturing efficiency of semiconductor devices.

Implementation Method 1

a silicide layer is then deposited to wrap over the source/drain feature

Methodology Applied
Scientific EffectPhysical Vapour Deposition: Physical Vapour Deposition

Implementation Method 2

The first interlayer dielectric layer and the first contact etch stop layer are etched to expose a top surface and sidewalls of the source/drain feature

Methodology Applied
Scientific EffectEtching:

Data Source

PatentUS20240290849A1Wrap-around silicide layer
Publication Date: 2024.08.29 TAIWAN SEMICONDUCTOR MANUFACTURING CO LTD
  • US20240290849A1 patent drawing
  • US20240290849A1 patent drawing
  • US20240290849A1 patent drawing

AI summary

Semiconductor structures and processes are provided. A semiconductor structure according to the present disclosure includes a channel region of a semiconductor body rising above an isolation feature, a gate structure wrapping over the channel region, a source/drain feature in contact with a sidewall of the channel region, a backside silicide layer disposed on a bottom surface of the source/drain feature, and a backside contact feature extending through the isolation feature to contact a bottom surface of the backside silicide layer. A sidewall of the backside contact feature is spaced apart from the isolation feature by a first backside contact etch stop layer (CESL) and a second backside CESL.