Wraparound Source Gate Structure for HEMT Leakage Suppression
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Solution Overview
Problem
High-voltage transistor devices, particularly high electron mobility transistors (HEMTs), experience unwanted leakage currents due to incomplete isolation by the isolation region, leading to sub-threshold humps in drain current vs. gate voltage relations, increased power consumption, and difficulty in modeling.
Innovation Solution
A gate structure is designed to wrap around the source contact, disrupting the underlying two-dimensional electron gas (2DEG) along a continuous path, thereby reducing leakage currents between the source and drain contacts.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If a conventional isolation region is used to separate source and drain contacts, then the device structure is simple and easy to manufacture, but leakage currents occur due to incomplete isolation
Solution Approach 1:
The gate structure is segmented into multiple portions that wrap around the source contact from different directions. This segmentation allows the gate to disrupt the 2DEG along a continuous path while maintaining manufacturing feasibility through standard photolithography processes.
Solution Approach 2:
The gate structure transitions from a conventional linear configuration to a wraparound configuration that extends in multiple dimensions around the source contact. This dimensional change enables complete disruption of the 2DEG path without significantly increasing manufacturing complexity.
2Loss of energy
If the gate structure wraps around the source contact to disrupt 2DEG, then leakage currents are reduced by up to 95%, but the device fabrication process becomes more complex
Solution Approach 1:
The wraparound gate structure serves multiple functions: it disrupts the 2DEG to reduce leakage, maintains control over the channel, and can be integrated with existing semiconductor fabrication processes. This multi-functionality justifies the increased fabrication complexity by delivering significant performance benefits.
Solution Approach 2:
The invention changes the geometric parameters of the gate structure (extending it around the source contact) to achieve superior electrical performance. This parameter change results in up to 95% reduction in leakage currents while the fabrication process remains compatible with standard semiconductor manufacturing techniques.
3Reliability
If the isolation region is extended to improve leakage suppression, then leakage currents are reduced, but the device area increases
Solution Approach 1:
The gate structure is merged with the source contact region by wrapping around it, rather than extending the isolation region separately. This merging achieves effective leakage suppression while utilizing the existing device area more efficiently, avoiding the need for additional isolation space.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The gate structure effectively mitigates leakage currents by up to 95%, reducing power consumption and improving modeling accuracy by minimizing sub-threshold humps in drain current.
Implementation Method 1
disrupting the underlying two-dimensional electron gas (2DEG) along a continuous path, thereby reducing leakage currents between the source and drain contacts
Data Source
AI summary
In some embodiments, the present disclosure relates to an integrated chip. The integrated chip includes a first source contact, a drain contact, and a first gate structure disposed over a substrate. The first gate structure is between the first source contact and the drain contact along a first direction. The first gate structure surrounds the first source contact. An isolation region is disposed within the substrate and surrounds an active area. A second gate structure surrounds a second source contact. The second gate structure is separated from the first gate structure by the drain contact. Both the first gate structure and the second gate structure are at least partially within the active area.