Wrapped-around Contact for Vertical FET Top Source-Drain
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Solution Overview
Problem
Current VFET integration schemes face issues with top source/drain contact over etching, leading to dielectric material over etching and subsequent gate shorts, which can be exacerbated by weak points in the dielectric material, and attempts to increase contact size can result in device shorts.
Innovation Solution
A method is developed to form a semiconductor structure with a top source/drain contact that surrounds the top source/drain region, using a protective liner and a top spacer to prevent over etching of the dielectric material between adjacent top source/drain regions, thereby preventing contact shorts and improving device reliability.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Manufacturing precision
If top source/drain contact over etch is performed to achieve desired contact dimensions, then contact landing is improved, but dielectric material over etching occurs causing gate shorts
Solution Approach 1:
A protective liner is deposited conformally over the top source/drain region before contact patterning. This preliminary protective layer prevents the etch process from penetrating into the dielectric material between adjacent top source/drain regions, thereby preventing gate shorts while still allowing the contact etch to achieve the desired dimensions through the protective liner.
Solution Approach 2:
The protective liner acts as an intermediary layer between the contact etch process and the dielectric material. It absorbs the harmful etching action, allowing the contact patterning to proceed with proper dimensions while the liner protects the underlying dielectric from over-etching that would cause gate shorts.
2Ease of manufacture
If dielectric material is over etched to expose top source/drain region, then contact formation is facilitated, but gate shorts are caused
Solution Approach 1:
The protective liner is deposited in advance before contact patterning, creating a controlled interface that allows the etch to reach the top source/drain region for contact formation while preventing the etch from continuing into the dielectric material, thus avoiding gate shorts.
Data Source
AI summary
A semiconductor structure and a method of making the same includes a first recessed region in a semiconductor structure, the first recessed region defining a first opening with a first positive tapering profile, as at least part of the first positive tapering profile, widening the first opening in a direction towards a top source/drain region of the semiconductor structure at a first tapering angle, and a top source/drain contact within the first opening, the top source/drain contact surrounding a surface of the top source/drain region. The semiconductor structure further includes a protective liner located at an interface between a bottom portion of the top source/drain region, a top spacer adjacent to the top source/drain region and a dielectric material between two consecutive top source/drain regions, the protective liner protects the top source/drain regions during contact patterning.