Wrapped Source-Drain Contacts for Tight Forksheet FET Spacing
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Solution Overview
Problem
Conventional semiconductor device fabrication faces challenges in tight spaces, particularly with high resistance and aspect ratios in front side vias, and AC performance issues due to parasitic capacitance in nanosheet structures, which affect signal transmission and cell height scaling.
Innovation Solution
The implementation of a fork sheet device with wrapped source and drain contacts and a power rail configuration that reduces resistance by increasing conductive area and aspect ratio, using a conductive contact that wraps around the source and drain structures and connects to a power bar, thereby enhancing signal transmission.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If front side contact schemes are used with conventional vias, then the device structure is simple, but the resistance is high and aspect ratio is problematic in tight spaces
Solution Approach 1:
The patent transitions from conventional vertical vias to a planar power bar structure that extends laterally beneath the nanosheet channels. This dimensional change allows the power delivery network to bypass the high-aspect-ratio via problem by distributing power through a low-resistance path in the same layer as the transistors, thereby improving signal transmission without requiring complex multi-layer via structures.
Solution Approach 2:
The power delivery network is segmented into multiple power bars, each serving specific nanosheet channels. This segmentation allows independent optimization of power delivery to different transistor regions, reducing overall resistance by providing multiple parallel power paths rather than relying on a single via structure.
2Productivity
If tighter spaces are used to increase device density, then productivity increases, but manufacturing precision becomes more difficult due to high aspect ratios
Solution Approach 1:
The patent extracts the power delivery function from the vertical via structure and relocates it to a lateral power bar structure. This extraction eliminates the need for high-aspect-ratio vias, allowing tighter spacing between devices without compromising manufacturing precision, as the power bar can be formed using standard planar deposition techniques rather than complex via etching and filling processes.
3Reliability
If conventional via structures are used, then the contact area is limited, but resistance remains high
Solution Approach 1:
The patent transitions from a vertical via structure with limited cross-sectional area to a lateral power bar structure with extended surface area. The power bar extends horizontally beneath multiple nanosheet channels, providing a large conductive area that significantly reduces resistance compared to conventional via structures, while maintaining compatibility with tight device spacing.
Data Source
AI summary
A microelectronic device includes a first source and drain structure adjacent to a second source and drain structure. A first conductive contact is in contact with a top surface and side surface of the first source and drain structure. A second conductive contact is in contact with a top surface and side surface of the second source and drain structure. The second conductive contact includes a via extension to connect to a backside component. A separating layer is located between the first conductive contact and the second conductive contact. A first sidewall of the separating layer is flush with the first conductive contact. A second sidewall of the separating layer is flush with the second conductive contact.