Wrapped Primary Gate HEMT Structure for Pinch-Off Control
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Solution Overview
Problem
High electron mobility transistors (HEMTs) suffer from performance degradation due to device size scaling, particularly experiencing pinch-off control issues and increased gate leakage, which affect their efficiency in RF and mmWave wireless applications.
Innovation Solution
A semiconductor structure with a d-mode HEMT featuring a multi-gate configuration, including a primary gate that wraps over a secondary gate with a P-type III-V semiconductor layer, which is floating, providing improved pinch-off control through a combination of vertically and horizontally oriented gate portions and a gate dielectric layer.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If device size scaling is implemented to improve integration density, then productivity increases, but performance degradation occurs due to pinch-off control issues and increased gate leakage
Solution Approach 1:
The gate structure is segmented into a primary gate and a secondary gate. The primary gate provides main control over the channel, while the secondary gate, positioned adjacent to the primary gate and extending along a portion of the channel, provides additional control. This segmentation allows independent optimization of each gate's function, enabling better pinch-off control and reduced gate leakage even in scaled devices.
Solution Approach 2:
The secondary gate is positioned in a different spatial dimension relative to the primary gate, specifically adjacent to and extending along a portion of the channel in a direction perpendicular to the primary gate's main control region. This dimensional arrangement creates overlapping control regions that enhance overall gate control without increasing the footprint area, thus maintaining integration density while improving performance.
2Reliability
If a multi-gate configuration is implemented to improve pinch-off control, then reliability improves, but device complexity increases
Solution Approach 1:
The secondary gate is strategically positioned to control specific regions of the channel where additional control is needed, rather than uniformly controlling the entire channel. This localized approach allows the multi-gate structure to provide enhanced pinch-off control only where necessary, reducing the overall complexity compared to a fully overlapping multi-gate configuration while still achieving improved reliability.
Data Source
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AI summary
A transistor on a substrate (101) includes a barrier layer (103) above the substrate and a multi-gate structure on the barrier layer. The multi-gate structure includes a primary gate (140) and a secondary gate (130). The secondary gate has opposing sidewalls, opposing end walls and a top surface. The primary gate includes essentially vertically-oriented first portions (140.1) on the barrier layer positioned laterally adjacent to opposing sidewalls (130.1), respectively, of the secondary gate. Optionally, the primary gate also includes an essentially horizontally-oriented second portion (140.2) on the top surface (130.2) of the secondary gate and/or essentially vertically-oriented third portions on the opposing end walls, respectively. The secondary gate can be a floating gate. Also disclosed is a method of forming the same.