Wrapped Gate JFET With Multiple Channels For High On-Off Ratio
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Solution Overview
Problem
Current semiconductor power amplifiers, particularly those using GaAs technologies, are costly due to the need for dedicated substrates and processing steps, and modified SiGe BiCMOS technologies add additional costs and complexity, making it challenging to achieve high power amplification with a high on/off impedance ratio in junction field effect transistors (JFETs).
Innovation Solution
A JFET structure with multiple semiconductor channels and a wrapped gate configuration, where the gate electrode surrounds the channels laterally and vertically, providing a large conduction area for high on-current and tight control for low off-current, formed in a standard CMOS substrate with shallow trench isolation and buried insulator layers for electrical isolation.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Ease of manufacture
If a JFET uses a conventional gate structure, then the manufacturing cost is reduced, but the on/off impedance ratio is insufficient for high power amplification
Solution Approach 1:
The gate electrode transitions from a planar configuration to a three-dimensional wrapped structure that surrounds the channel in multiple dimensions. This wrapped gate extends laterally along the channel and vertically through different depths, creating a multi-dimensional control structure that significantly enhances the on/off impedance ratio while remaining compatible with CMOS manufacturing processes
Solution Approach 2:
The gate electrode is configured to wrap around and surround the channel, with the gate structure nested along the channel length and penetrating through different vertical levels. This nested configuration allows the gate to control the channel from multiple spatial perspectives, achieving superior impedance characteristics without requiring separate processing steps
2Power
If the cross-sectional area of the channel is increased to decrease impedance in the on state, then the on-current increases, but the leakage current through the channel increases
Solution Approach 1:
The wrapped gate structure creates locally enhanced electric field control at critical regions along the channel. By positioning gate material in specific three-dimensional locations surrounding the channel, the structure provides stronger local control where needed to suppress leakage while maintaining larger overall channel cross-sectional area for high on-current capability
Solution Approach 2:
The gate control extends into the vertical dimension and wraps around the channel laterally, creating multi-dimensional control over the current flow. This allows the channel to maintain a large horizontal cross-sectional area for high on-current while the vertically extending gate portions provide enhanced suppression of leakage currents through improved electric field control
3Power
If GaAs technology is used for high-end power amplifiers, then the power amplification performance is improved, but the manufacturing cost increases due to dedicated substrates and processing steps
Solution Approach 1:
The wrapped gate JFET structure is designed to be universally compatible with standard CMOS silicon substrates and processing technologies. This universal design allows the device to achieve high power amplification performance using existing, cost-effective CMOS manufacturing infrastructure, eliminating the need for expensive GaAs substrates and dedicated processing steps while maintaining high performance characteristics
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
The JFET structure achieves high on-current for power amplification while maintaining high impedance in the off-state, reducing manufacturing costs and integrating seamlessly with standard CMOS technologies, thus addressing the need for efficient and cost-effective power amplification.
Implementation Method 1
the body of the transistor and the gate of the transistor form a reverse-biased pn junction with depletion regions both in the gate and in the body
Implementation Method 2
A typical JFET comprises a source and a drain that are heavily doped with dopants of a first conductivity type... The gate, located on the body and separated from the source and the drain, is heavily doped with dopants of a second conductivity type
Data Source
AI summary
A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.