Wrapped Gate High-k Stack for Threshold Voltage Tuning
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Solution Overview
Problem
Conventional semiconductor devices face challenges in tuning threshold voltages as the device scaling down process makes it difficult to increase work function metal thickness, leading to high gate resistance and manufacturing difficulties, especially in advanced technology nodes where gate fill window for multiple threshold voltage tuning is restricted.
Innovation Solution
The proposed solution involves improving the gate fill window and reducing gate resistance by selectively driving specific metal or boron ions into a high-k dielectric layer of the gate structure at various concentrations to tune threshold voltages, and including a second high-k dielectric layer to reduce gate leakage, along with work function barrier layers of different thicknesses to achieve flexible threshold voltage tuning.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If work function metal thickness is increased to tune threshold voltages, then threshold voltage tuning capability is improved, but gate resistance increases and manufacturing becomes difficult
Solution Approach 1:
The gate structure is segmented into multiple functional layers: a first high-k dielectric layer for threshold voltage tuning via dopant concentration, a second high-k dielectric layer for leakage reduction, and a work function metal layer. This segmentation allows each layer to perform its specific function optimally without compromising other parameters.
Solution Approach 2:
The first high-k dielectric layer has spatially varying dopant concentrations (e.g., graded doping profiles) to achieve different threshold voltages in different regions. This local variation in composition enables threshold voltage tuning without requiring changes to the overall gate structure or metal thickness.
2Productivity
If device geometry is scaled down to increase functional density, then production efficiency is improved, but gate fill window for threshold voltage tuning is restricted
Solution Approach 1:
The patent transitions from two-dimensional planar gates to three-dimensional wrapped gate structures that surround the channel on multiple sides. This dimensional change increases the effective gate control and fill window while maintaining compatibility with scaled device dimensions, allowing threshold voltage tuning without sacrificing productivity.
Solution Approach 2:
The gate structure uses composite materials combining high-k dielectric layers with different dopant concentrations and a work function metal layer. This composite approach enables multiple threshold voltage tuning options within a single gate structure, maintaining adaptability even as device geometry scales down.
3Adaptability or versatility
If work function metal thickness is increased to tune threshold voltages, then threshold voltage tuning capability is improved, but manufacturing precision becomes difficult
Solution Approach 1:
Instead of adjusting work function metal thickness to tune threshold voltages, the patent changes the dopant concentration parameter in the high-k dielectric layer. This parameter change achieves threshold voltage tuning without requiring precise control of metal layer thickness, thereby improving manufacturing precision while maintaining tuning capability.
Applied Scientific Principles
This section explains which scientific principles are used to turn an abstract innovation direction into a practical engineering solution.
Function Achieved in This Case
This approach enhances the flexibility in tuning threshold voltages and reduces gate leakage, improving the manufacturing process by maintaining a large gate fill window and achieving lower gate resistance.
Implementation Method 1
selectively driving specific metal or boron ions into a high-k dielectric layer of the gate structure at various concentrations to tune threshold voltages
Implementation Method 2
including a second high-k dielectric layer to reduce gate leakage
Data Source
AI summary
A device comprises a substrate, a semiconductor channel over the substrate, and a gate structure over and laterally surrounding the semiconductor channel. The gate structure comprises a first dielectric layer comprising a first dielectric material including dopants. A second dielectric layer is on the first dielectric layer, and comprises a second dielectric material substantially free of the dopants. A metal fill layer is over the second dielectric layer.