3D IC Wrapper Cell for Interconnect Delay Defect Testing
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Solution Overview
Problem
Existing 3D stacked ICs face challenges in testing for manufacturing defects, particularly delay defects in inter-die interconnects, which are not adequately covered by current design-for-testing solutions, leading to potential functional failures.
Innovation Solution
A wrapper cell system that enables standardized testing for delay defects, incorporating a test access mechanism and modular design to support DC, AC, and burn-in tests, reducing the need for external testers and allowing for plug-n-play stacking, self-aware logic, and high toggling capabilities.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional static (DC) test using wrappers is used for inter-die interconnects, then hard opens and shorts can be tested, but delay defects and other manufacturing defects are not covered
Solution Approach 1:
The wrapper cell is designed to perform multiple test functions including DC tests for hard opens/shorts, AC tests for delay defects, and burn-in tests, making it a universal test structure that covers all interconnect defect types rather than being limited to static fault models only
2Manufacturing precision
If existing DfT solutions are used for 3D stacked ICs, then manufacturing defects can be tested, but delay defects in inter-die interconnects remain undetected
Solution Approach 1:
The test structure incorporates dynamic AC testing capabilities that can detect delay defects by applying time-varying test patterns and measuring temporal response, moving beyond static DC testing to dynamically characterize interconnect performance and detect timing-related manufacturing defects
3Reliability
If comprehensive testing for all defect types is implemented, then product quality improves, but test system complexity and external tester requirements increase
Solution Approach 1:
The wrapper cell incorporates self-service test capabilities where the interconnect under test is tested using signals generated and captured within the same wrapper structure, enabling the system to perform its own testing without requiring complex external test equipment for all test types
4Reliability
If inter-die interconnects are made more robust to prevent defects, then reliability improves, but manufacturing flexibility and design freedom are reduced
Solution Approach 1:
The test structures and methodologies are built into the design phase and manufacturing process, allowing defects to be detected early during testing rather than requiring over-engineered robust interconnect designs, thus maintaining manufacturing flexibility while ensuring reliability through comprehensive testing
Data Source
AI summary
A test circuitry for testing an interconnection between interconnected dies includes a cell embedded within one of the dies. The cell includes a selection logic module that includes a first multiplexer configured to receive a first control signal and provide a first output test signal, and a second multiplexer configured to receive a second control signal and provide a second output test signal. The cell includes a scannable data storage module coupled to the first multiplexer; and a transition generation module configured to receive a third control signal; wherein the first and second output test signals are generated based on respective states of the first, second, and third control signals, and wherein the test circuitry is configured to use the first and second output test signals to perform at least two of: a DC test on the interconnection, an AC test on the interconnection, and a burn-in-test on the interconnection.