Wrapper Cell Scan Chain for IC Test Coverage
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Solution Overview
Problem
Conventional scan testing techniques for integrated circuits with multiple cores, such as those in hard disk drives, face challenges in achieving complete test coverage of functional paths due to inefficiencies in area and timing, leading to increased size, cost, and reduced diagnostic resolution.
Innovation Solution
The implementation of an area and timing efficient wrapper cell scan chain configuration between circuitry cores, utilizing multiplexers and non-resettable flip-flops that operate as part of the scan shift path but not the functional path, allowing for separate scan testing of each core and comprehensive test coverage.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional wrapper cell designs are used to form scan chains around circuitry cores, then test coverage of interconnect paths between cores is improved, but area and timing efficiency deteriorates, leading to increased size and cost
Solution Approach 1:
The patent changes the operational parameters of the wrapper cell flip-flops by making them non-resettable and configuring their throughput data paths to be part of the scan shift path but not the functional path. This parameter change allows the same hardware structure to serve dual purposes: maintaining test coverage while reducing area and timing overhead by eliminating redundant reset logic and optimizing the data path configuration
2Reliability
If conventional wrapper cell designs are used to form scan chains around circuitry cores, then test coverage of interconnect paths between cores is improved, but timing efficiency deteriorates, impacting performance
Solution Approach 1:
The patent extracts the reset functionality from the wrapper cell flip-flops, creating non-resettable flip-flops. This extraction eliminates the reset logic and associated timing constraints from the wrapper cells, thereby improving timing efficiency and performance while preserving the essential test coverage function through the scan chain configuration
3Loss of time
If high levels of scan compression are used, then test time is reduced, but diagnostic resolution deteriorates, reducing ability to attribute failures to exact faults
Solution Approach 1:
The patent segments the test architecture by implementing separate scan chains for different functional paths: wrapper cells test interconnect paths between cores, while separate scan chains test internal core logic. This segmentation allows independent optimization of each chain, enabling use of compression techniques on core-internal chains without compromising the diagnostic resolution of interconnect path testing through the wrapper cells
Data Source
AI summary
An integrated circuit comprises scan test circuitry and additional circuitry subject to testing utilizing the scan test circuitry. The scan test circuitry comprises a plurality of scan chains, including at least one wrapper cell scan chain arranged between first and second circuitry cores of the additional circuitry, with the wrapper cell scan chain comprising a plurality of wrapper cells and being configurable to operate as a serial shift register in a scan shift mode of operation. At least one of the wrapper cells of the wrapper cell scan chain comprises a flip-flop having a throughput data path that is part of a scan shift path of the wrapper cell scan chain and not part of a functional path between the first and second circuitry cores. In an HDD controller embodiment, the first and second circuitry cores may comprise respective read channel and additional cores of a system-on-chip.