Wrapper Chain State-Machine Flops for Delay-Immune IC Testing
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Solution Overview
Problem
Integrated circuits face challenges in testing due to signal transmission delays in wrapper chains, which can lead to undefined states and timing issues during the capture phase, making it difficult to accurately test the core logic.
Innovation Solution
The implementation of state machine-driven multi-flop logic elements in input and output wrapper chains, which are individually configurable to output pre-selected values, allowing them to operate independently of input signals and mitigate the effects of slow connections by configuring in programmable operational modes such as maintain or toggle modes.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If conventional flops are used in wrapper chains, then the structure is simple, but signal transmission delays cause undefined states during capture phase
Solution Approach 1:
The wrapper chain is segmented into multiple independent state machine-driven flops, each capable of autonomous operation. This segmentation allows each flop to manage its own state transitions independently, eliminating the propagation of timing errors from slow connections while maintaining overall system functionality.
Solution Approach 2:
The flops are transformed from static, fixed-function elements into dynamic state machine-driven units that can adapt their behavior based on operational phase. Each flop dynamically switches between capture mode, hold mode, and shift mode, allowing the wrapper chain to optimize performance for each specific operation and compensate for connection delays.
2Reliability
If state machine-driven multi-flop logic elements are implemented, then immunity to transmission delays is achieved, but device complexity increases
Solution Approach 1:
Each state machine-driven flop is designed as a universal logic element that performs multiple functions: data capture, state holding, and sequential shifting. This multi-functionality consolidates what would otherwise require separate circuitry for each operation, reducing overall complexity while providing robust immunity to transmission delays through autonomous state management.
Solution Approach 2:
The state machine-driven flops are self-sufficient units that autonomously manage their own state transitions and data capture without requiring external timing control. Each flop independently monitors its input conditions and automatically executes the appropriate state transition, eliminating the need for complex external synchronization circuitry to compensate for transmission delays.
3Ease of operation
If flops are connected in series in wrapper chains, then data flow is simplified, but slow interconnects cause timing issues
Solution Approach 1:
The state machine-driven flops perform preliminary state preparation and data validation before actual data capture. By pre-establishing correct state transitions and validating input conditions in advance, the system compensates for subsequent transmission delays, ensuring that timing-critical operations complete successfully despite slow interconnects.
Data Source
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AI summary
Integrated circuits are described that utilize internal state machine-driven logic elements (e.g., flops) within input and/or output wrapper chains that are used to test internal core logic of the integrate circuit. One or more individual logic elements of the wrapper chains within the integrated circuit is implemented as a multi-flop state machine rather than a single digital flip-flop. As multi-flop state machines, each enhanced logic element of a wrapper chain is individually configurable to output preselected values so as to disassociate the state machine-driven flops from signal transmission delays that may occur in the input or output wrapper chains of the integrated circuit.