Wrapper Circuit for Hard Macro and User Logic Width Mismatch
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Solution Overview
Problem
The performance of PCIe Endpoint designs instantiated in FPGA fabric is limited, necessitating enhanced performance within programmable logic devices.
Innovation Solution
An integrated circuit with a core having a transaction interface of one bit width and user logic with a smaller bit width, coupled via a wrapper circuit that alternates data pairs between clock signals to optimize data transfer between hard macros and user logic, allowing for reduced pin usage and frequency adjustment.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If PCIe Endpoint design is instantiated in FPGA fabric using soft core, then device complexity is reduced and ease of manufacture is improved, but performance and bandwidth are limited
Solution Approach 1:
The patent segments the PCIe interface implementation by separating the high-performance hard macro core from the configurable user logic interface. The hard macro provides the performance-critical PCIe endpoint functionality while the user logic handles application-specific requirements, allowing each to be optimized independently for their respective functions.
Solution Approach 2:
The patent introduces a wrapper circuit as an intermediary between the hard macro core and user logic. This wrapper handles the bit width conversion and interface compatibility, allowing the high-performance hard macro to communicate efficiently with diverse user logic interfaces without compromising performance or requiring complex reconfiguration of the core itself.
2Productivity
If hard macro with larger bit width transaction interface is used, then bandwidth and performance are improved, but pin requirements and routing complexity increase
Solution Approach 1:
The patent resolves the pin requirement contradiction by transitioning from a spatial solution (more physical pins) to a temporal solution (time-multiplexed data transfer). The wrapper circuit achieves high bandwidth by rapidly alternating between different data pairs across the same physical interface, effectively creating additional data pathways through time division rather than requiring additional physical pins.
3Adaptability or versatility
If fixed bit width interface is used between hard macro and user logic, then interface simplicity is improved, but adaptability to different user logic requirements deteriorates
Solution Approach 1:
The patent employs parameter changes by making the wrapper circuit's interface characteristics configurable. The wrapper can be configured to match different user logic interface requirements (such as different bit widths, clock domains, or timing requirements) while maintaining a consistent high-performance interface to the hard macro core, thus providing adaptability without requiring multiple specialized interface designs.
Data Source
AI summary
A hard macro-to-user logic interface of an integrated circuit is described. The integrated circuit includes a core as an application specific circuit block with a transaction interface of a first bit width and includes programmable logic capable of being programmed to instantiate user logic. The user logic has a user interface of a second bit width substantially less than the first bit width. A wrapper circuit couples the user interface and the transaction interface for coupling the core to the user logic.