Wrapper Module for Mixed Language Circuit Design Bind Commands
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Solution Overview
Problem
In mixed language environments for electronic design automation, the execution of System Verilog bind commands often leads to errors due to the lack of full functionality support, especially when higher-level design units are written in different hardware design languages like VHDL or System C, resulting in incomplete interface instantiation.
Innovation Solution
The implementation of tools and mechanisms that generate wrapper modules and bind statements to facilitate the instantiation of assertion modules across different hardware design languages, ensuring full functionality and error-free interface creation in mixed language environments.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Adaptability or versatility
If System Verilog bind commands are executed in mixed language environments, then instantiation of assertion modules is enabled, but errors occur due to lack of full functionality support
Solution Approach 1:
The patent introduces a wrapper module as an intermediary between the System Verilog assertion module and the target module written in a different hardware design language. The wrapper module acts as a mediator that translates and adapts the bind command interface, enabling cross-language instantiation while maintaining execution reliability by handling language-specific syntax and functionality differences.
2Ease of manufacture
If bind commands are used to instantiate lower-level design units in higher-level design units, then code modification is avoided, but functionality is lost in mixed language environments
Solution Approach 1:
The patent segments the instantiation process into two parts: the original higher-level design unit code remains unchanged (maintaining ease of manufacture), while a separate wrapper module is created to handle the bind command functionality. This segmentation allows the bind command to work in mixed language environments without modifying the original design unit code, thus preserving both ease of manufacture and adaptability.
3Device complexity
If direct instantiation of assertion modules is performed in target modules, then interface creation is simplified, but errors occur due to language incompatibility
Solution Approach 1:
The wrapper module serves as an intermediary that simplifies interface creation while ensuring reliability. It provides a standardized interface between the assertion module and target module, handling language incompatibility issues automatically. This approach maintains low interface instantiation complexity while improving reliability through proper language bridging.
Data Source
AI summary
This application discloses a computing system configured to determine that a first bind command is configured to prompt instantiation of an assertion module in a target module of a circuit design, which creates a mixed-language environment for the circuit design. The computing system, in response to the determination that the first bind command is configured to create the mixed-language environment for the circuit design, configured to generate a wrapper module configured to prompt instantiation of the assertion module in the wrapper module. The computing system configured to generate a second bind command configured to prompt instantiation of the wrapper module in the target module.