Wreal Net Coercion for Mixed-Signal HDL Interoperability

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Solution Overview

Problem

The existing Verilog-AMS discipline resolution process fails to effectively compute connectivities and identify analog and digital partitions in mixed-signal designs containing blocks written in different HDLs, particularly when IP blocks from various vendors are connected, leading to issues with multiple drivers driving wreal nets and limitations in coercion of non-Verilog-AMS blocks.

Innovation Solution

A computer system executes driver resolution processes to select and apply appropriate driver resolution methods for wreal nets with multiple drivers, and performs wreal coercion to convert wire type nets to wreal nets, enabling simulation of integrated circuit designs with blocks from different HDLs by resolving values and ensuring compatibility across different hierarchical levels.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Adaptability or versatility

If the existing Verilog-AMS discipline resolution process is used, then simulation of integrated circuits can be performed, but it fails to effectively compute connectivities and identify analog and digital partitions in mixed-signal designs containing blocks written in different HDLs

Engineering Contradiction:

Improvecompatibility with different HDLsVSAvoidconnectivity computation accuracy

Core Design Contradiction:

Adaptability or versatilityVSLoss of information

Solution Approach 1:

The patent introduces a discipline information propagation mechanism that acts as an intermediary between blocks written in different HDLs. This mechanism propagates discipline information (analog/digital partitioning) through hierarchical levels and across HDL boundaries, enabling the simulation process to correctly identify analog and digital partitions even when blocks from different vendors are connected, thus resolving the connectivity computation issue without sacrificing compatibility

Inventive Principle:

Principle #24Intermediary (Mediator)

2Adaptability or versatility

If multiple drivers are allowed to drive wreal nets, then more flexible design connections are possible, but the existing process cannot resolve the multiple driver values leading to simulation errors

Engineering Contradiction:

Improvedesign connection flexibilityVSAvoidsimulation correctness

Core Design Contradiction:

Adaptability or versatilityVSReliability

Solution Approach 1:

The patent applies preliminary action by resolving multiple driver values on wreal nets before the simulation execution phase. The discipline information propagation mechanism预先 establishes the correct connectivity and partitioning information, allowing the simulation process to handle multiple drivers correctly by knowing in advance which nets are analog and which are digital, thus preventing simulation errors while maintaining design flexibility

Inventive Principle:

Principle #10Preliminary action

Solution Approach 2:

The patent implements a feedback mechanism where discipline information is propagated from lower hierarchical levels back to higher levels, and from blocks with known discipline information to blocks that need it. This feedback loop ensures that all blocks in the mixed-signal design have the correct discipline information, enabling reliable simulation of designs with multiple drivers driving wreal nets

Inventive Principle:

Principle #23Feedback

3Adaptability or versatility

If non-Verilog-AMS blocks are coerced to wreal format, then connectivity between different HDL blocks is enabled, but the existing coercion process is limited and cannot handle blocks from different vendors or encrypted blocks

Engineering Contradiction:

Improveinteroperability across vendorsVSAvoidcoercion process complexity

Core Design Contradiction:

Adaptability or versatilityVSDevice complexity

Solution Approach 1:

The patent makes the discipline information propagation mechanism universal by designing it to work across different HDLs (Verilog, VHDL, SystemVerilog) and different simulation tools. The mechanism propagates discipline information through standard interfaces and hierarchical structures that are common to all HDLs, enabling non-Verilog-AMS blocks from any vendor to be coerced to wreal format without increasing process complexity, thus achieving vendor-agnostic interoperability

Inventive Principle:

Principle #6Universality (Multi-functionality)

Data Source

PatentUS8255191B1Using real value models in simulation of analog and mixed-signal systems

Publication Date: 2012.08.28 CADENCE DESIGN SYST INC

AI summary

A method is provided to coerce a wire type net in an integrated circuit design to become a wreal net in the design, comprising: running a wreal coercion process on a computer system including the acts of, identifying a wire type net that is connected to a wreal net in an integrated circuit design; and converting the identified wire type net to a wreal net.