NAND Flash Write Abort Recovery Using Cross-Word-Line Parity

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Solution Overview

Problem

Existing data storage devices face challenges in recovering corrupted data due to write abort events, where error correcting codes (ECC) are insufficient, leading to data loss and increased bit error rates, and conventional recovery techniques require significant memory and processing resources or result in performance degradation.

Innovation Solution

A write abort recovery technique that uses both reliable and unreliable bits from a corrupted page to recover data by generating parity information through XOR operations between bits written to different word lines, reducing the need for extensive backup data and minimizing performance impact.

Engineering Contradictions & Design Principles

VSEngineering Contradiction Analysis

1Reliability

If conventional backup techniques are used to back up each bit of lower page data, then data recovery capability is improved, but memory usage and processing resources are significantly increased

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidmemory usage
Core Design Contradiction:
ReliabilityVSQuantity of substance

Solution Approach 1:

The patent combines lower page data from multiple word lines and generates compact parity information that represents the combined data state. This merging approach allows recovery of corrupted data from any single word line using the parity information and data from other word lines, achieving full recovery capability with minimal overhead (only 1/4 the memory of conventional backup methods).

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

Instead of creating full backups of lower page data, the patent creates a simplified copy in the form of parity information generated through XOR operations. This parity copy is sufficient for recovery purposes and uses only 1/4 the memory of conventional full backup techniques.

Inventive Principle:
Principle #26Copying

2Reliability

If full backup of lower page data is performed, then data recovery capability is improved, but system performance is degraded due to increased processing resources

Engineering Contradiction:
Improvedata recovery capabilityVSAvoidsystem performance
Core Design Contradiction:
ReliabilityVSProductivity

Solution Approach 1:

The patent merges lower page data from multiple word lines and generates compact parity information through XOR operations. This approach reduces processing overhead during normal operation compared to conventional full backup methods, while enabling complete data recovery when write abort events occur.

Inventive Principle:
Principle #5Merging (Combining)

Solution Approach 2:

The patent creates a simplified parity copy instead of full data backups, significantly reducing the processing resources required for data protection and recovery operations, thereby improving overall system performance.

Inventive Principle:
Principle #26Copying

3Quantity of substance

If parity information is generated from multiple word lines, then backup data overhead is reduced, but the complexity of data recovery processing is increased

Engineering Contradiction:
Improvebackup data overheadVSAvoiddata recovery processing complexity
Core Design Contradiction:
Quantity of substanceVSDevice complexity

Solution Approach 1:

The patent segments lower page data across multiple word lines (e.g., WL0-WL3) and generates parity information by XORing corresponding bits from each word line. During recovery, the system reads data from uncorrupted word lines and applies the same XOR operations with the parity information to reconstruct corrupted data, making the process systematic and manageable.

Inventive Principle:
Principle #1Segmentation

Solution Approach 2:

The patent uses parity information as an intermediary that mediates between multiple word lines. This intermediary contains the combined information needed to recover any single corrupted word line when combined with data from other word lines, simplifying the recovery process despite the multi-word-line architecture.

Inventive Principle:
Principle #24Intermediary (Mediator)

4Stability of the object's composition

If lower page data is written to multiple word lines, then data distribution is improved, but the risk of corruption from write abort events is increased

Engineering Contradiction:
Improvedata distributionVSAvoidcorruption risk
Core Design Contradiction:
Stability of the object's compositionVSReliability

Solution Approach 1:

The patent performs preliminary actions by generating and storing parity information from multiple word lines before write abort events can occur. This parity information serves as a pre-computed safety mechanism that enables recovery of any corrupted word line, transforming the potential vulnerability of multi-word-line storage into a recoverable configuration.

Inventive Principle:
Principle #10Preliminary action

Solution Approach 2:

The patent converts the potential harm of write abort events (which can corrupt lower page data) into a benefit by using the same multi-word-line architecture to enable recovery. The parity information, generated from distributing data across multiple word lines, becomes the key to recovering from write abort corruptions, turning the distributed architecture's vulnerability into its strength.

Inventive Principle:
Principle #22Blessing in disguise (Convert harm into benefit)

Data Source

PatentUS9229801B2Method and device for write abort protection
Publication Date: 2016.01.05 SANDISK TECHNOLOGIES LLC
  • US9229801B2 patent drawing
  • US9229801B2 patent drawing
  • US9229801B2 patent drawing

AI summary

A data storage device includes a non-volatile memory and a controller. A method includes receiving first data and second data from a host device. A first error-correcting code (ECC) codeword associated with the first data is written to a first word line of the non-volatile memory, and a second ECC codeword associated with the second data is written to a second word line of the non-volatile memory. The first ECC codeword includes a first bit and a second bit, and the second ECC codeword includes a third bit and a fourth bit. The method further includes writing parity information to a parity storage portion of the non-volatile memory that is distinct from the first word line and from the second word line. The parity information includes a parity bit that is based on the first bit, the second bit, the third bit, and the fourth bit.