Write Address Delay Circuit for Encrypted Memory Read Latency
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Solution Overview
Problem
In data storage systems where write data is encrypted prior to storage, the delay in L-to-P mapping and encryption processes leads to write addresses blocking subsequent read requests, resulting in increased read latency.
Innovation Solution
Implementing a delay circuit to align the output of physical addresses with encrypted write data, ensuring media control circuits are available for other requests during encryption, by delaying the input of logical addresses.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Reliability
If write data is encrypted prior to storage and L-to-P mapping is performed, then data security is improved, but read latency increases due to address blocking
Solution Approach 1:
The patent applies preliminary action by pre-calculating and storing mapping relationships between logical addresses and encryption parameters before actual write operations. The control circuit maintains a mapping table that stores logical address to encryption key mappings, allowing read operations to retrieve decryption information without waiting for encryption/decryption processes to complete, thereby reducing read latency while maintaining data security
Solution Approach 2:
The patent introduces an intermediary mapping table structure that decouples the read path from the encryption/decryption process. The mapping table acts as an intermediary layer that provides pre-computed address translations and encryption parameters, allowing the media control circuit to initiate read operations independently without being blocked by ongoing encryption or decryption operations
2Productivity
If physical address output is delayed to align with encrypted write data, then media control circuit availability is improved, but write operation complexity increases
Solution Approach 1:
The patent applies preliminary action by pre-computing and buffering physical addresses before they are needed for write operations. The control circuit prepares the mapping between logical and physical addresses in advance, allowing the media control circuit to be released and handle other requests during the encryption process, then quickly resume write operations when encryption completes without complex real-time coordination
Solution Approach 2:
The patent introduces a buffer or intermediary storage mechanism that temporarily holds physical addresses and write data. This intermediary structure decouples the address generation process from the encryption process, allowing independent optimization of each operation and simplifying the overall control logic by eliminating the need for complex real-time synchronization between address output and data encryption
Data Source
AI summary
An apparatus includes control circuits configured to connect to a memory structure. The control circuits are configured to receive a write request that includes a logical address with write data corresponding to the logical address, encrypt the write data to obtain encrypted write data and map the logical address to a physical address in the memory structure. The control circuits are further configured to delay output of the physical address by a delay period to align output of the physical address and the encrypted write data.