Write Assist Circuit Mitigates Bit Line Loading in SRAM Arrays
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Solution Overview
Problem
In memory systems, the varying physical distances between input/output circuits and memory cells result in different resistive and capacitive loads for each cell in a column, affecting write operations and leading to potential write errors and reduced write speed.
Innovation Solution
A write assist (WAS) circuit is formed by modifying three memory cells with a standard six-transistor configuration, using memory-adapted transistors to mitigate resistive and capacitive loading issues, and is powered by voltage levels from the memory power-domain to assist in write operations.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Quantity of substance
If memory cells are arranged in an array with varying physical distances from I/O circuit, then memory capacity is increased, but resistive and capacitive load varies for each cell affecting write operations
Solution Approach 1:
The patent applies local quality by providing different write assist circuit configurations for different column groups based on their distance from the I/O circuit. Columns closer to the I/O circuit receive one configuration while columns farther away receive a different configuration, optimizing write operations for each location's specific electrical characteristics.
Solution Approach 2:
The patent changes electrical parameters (threshold voltage, transistor size, drive strength) of the write assist circuit transistors based on the column's position in the array. This allows the circuit to adapt to varying resistive and capacitive loads at different physical locations, maintaining reliable write operations across the entire memory array.
2Ease of manufacture
If standard six-transistor memory cell configuration is used, then manufacturing simplicity is maintained, but write speed is reduced due to resistive and capacitive loading
Solution Approach 1:
The patent introduces a write assist circuit as an intermediary between the I/O circuit and the memory cells. This intermediary provides additional drive current to overcome resistive and capacitive loading effects, enabling faster write operations without modifying the standard six-transistor memory cell configuration itself.
Solution Approach 2:
The patent merges the write assist circuit with the memory cell column structure by sharing bit lines and integrating the assist transistors into the existing column architecture. This combination achieves write speed improvement while maintaining manufacturing simplicity through unified fabrication processes.
3Reliability
If write assist circuit is added to mitigate loading issues, then write operation reliability is improved, but device complexity increases
Solution Approach 1:
The write assist circuit is designed to perform multiple functions: it provides write drive current, performs write leveling to equalize voltage across bit lines, and adapts to different column positions. This multi-functionality reduces the need for separate dedicated circuits for each function, thereby limiting the increase in overall device complexity.
Solution Approach 2:
The patent segments the memory array into different column groups that require different write assist configurations. This segmentation allows each segment to be optimized independently, preventing the need for overly complex universal circuits that would be required to handle all variations within a single unified design.
4Ease of manufacture
If voltage levels are not equalized across bit lines, then manufacturing simplicity is maintained, but write errors increase due to inconsistent voltage levels
Solution Approach 1:
The patent implements equipotentiality by using the write assist circuit to equalize voltage levels across all bit lines before write operations. The circuit ensures that each bit line starts at the same voltage potential, eliminating write errors caused by voltage mismatches while maintaining manufacturing simplicity through standard fabrication processes.
Data Source
AI summary
A memory system includes a first array (of memory cells) and a second array (of write assist circuits) arranged into columns each including a bit line and a bit_bar line coupled to corresponding memory cells of the first array and a corresponding at least one write assist circuit of the second array, each write assist circuit including: latch and memory-adapted third and fourth NMOS transistors. The latch includes: memory-adapted first PMOS and first NMOS transistors connected in series between a power-supply voltage and a first node selectively connectable to a ground voltage; and memory-adapted second PMOS transistor and second NMOS transistors connected in series between the power-supply voltage and a second node selectively connectable to ground voltage. The third NMOS transistor is connected in series between the first node and ground voltage; and the fourth NMOS transistor connected in series between the second node and ground voltage.