Write Assist Circuitry for SRAM Voltage Control
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Solution Overview
Problem
Conventional schemes for lowering core voltage supply (Vddc) in memory applications face challenges such as high DC power aggregation and large area penalties, making them difficult to implement effectively.
Innovation Solution
A negative feedback based core supply lowering scheme for write assist in static random access memory (SRAM) applications, which utilizes a write assist circuitry with column selector, discharge, feedback, and trigger circuits to operate within a negative feedback system, reducing Vddc without a DC current path and minimizing area overhead.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Use of energy by moving object
If a voltage divider is used to generate an intermediate voltage value lower than full core voltage supply, then the core voltage supply (Vddc) is lowered for write assist, but huge DC power aggregation occurs during generation of the intermediate voltage in each bitcell column, resulting in huge dynamic power during write operation
Solution Approach 1:
The patent extracts and removes the harmful DC current path from the write assist circuitry. By eliminating the direct DC path between the voltage divider and ground in each bitcell column, the scheme prevents DC power aggregation while still achieving the desired voltage lowering effect through alternative charge sharing mechanisms that do not sustain continuous current flow.
Solution Approach 2:
The patent implements periodic charge sharing between fully charged Vddc nodes and pre-discharged capacitors during write operations. This periodic action occurs only when needed for write assist, rather than continuously, thereby reducing dynamic power consumption while still achieving the necessary voltage lowering effect during critical write operations.
2Loss of energy
If charge sharing between fully charged Vddc and a pre-discharged capacitor with assist of a route over a core bitcell array is used, then DC current path is avoided, but area penalty is significantly large
Solution Approach 1:
The patent merges the write assist functionality with existing bitcell structures by utilizing the core bitcell array itself as part of the charge sharing path. By combining the assist circuitry with the existing memory array structure rather than adding separate dedicated assist circuits, the area overhead is significantly reduced while still achieving the desired charge sharing effect.
Solution Approach 2:
The patent makes the core bitcell array serve multiple functions: it acts as both the storage element and the charge sharing path for write assist operations. This multi-functionality eliminates the need for dedicated assist circuitry with large area overhead, as the existing array structures are reused for both memory storage and voltage assistance during writes.
3Use of energy by moving object
If conventional write assist schemes are implemented, then core voltage supply (Vddc) is lowered, but implementation difficulty increases due to huge DC power aggregation and large area penalty
Solution Approach 1:
The patent implements a feedback mechanism that monitors the voltage levels and controls the charge sharing process accordingly. This feedback control ensures that write assist is activated only when necessary and regulates the charge sharing to prevent excessive DC power aggregation, thereby simplifying implementation while achieving the desired voltage lowering effect.
Data Source
AI summary
Various implementations described herein are directed to an integrated circuit having core circuitry with an array of memory cells arranged in columns. The integrated circuit may include write assist circuitry having a column selector that accesses the memory cells via a bitline coupled to each of the columns. The write assist circuitry may include a first node that couples the column selector to a discharge circuit and a feedback circuit. The write assist circuitry may include a second node that couples a trigger circuit to the discharge circuit and the feedback circuit. The trigger circuit enables the discharge circuit, discharges the second node, and is disabled after discharging the second node. The discharge circuit discharges the first node, and the feedback circuit tracks the first node and disables the discharge circuit.