Write Assist Driver Circuit for Low Voltage Memory Write Reliability
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Solution Overview
Problem
Conventional memory devices face reliability issues when writing to memory cells at low voltage levels due to unstable transistor behavior, leading to improper operation and inhibited writeability.
Innovation Solution
A memory circuit with a write assist driver circuit that provides a lowered memory supply voltage to the bit cell core and local write bitlines during write operations, while maintaining a higher voltage for the memory core, ensuring correct write operations even at reduced voltages.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Loss of energy
If the operating voltage is lowered to achieve power efficiency, then power consumption is reduced, but writeability and reliability of memory cells deteriorate due to unstable transistor behavior
Solution Approach 1:
The memory device is divided into two distinct voltage domains: a first voltage domain for the memory core circuitry operating at a higher voltage level, and a second voltage domain for peripheral circuits operating at a lower voltage level. This segmentation allows each domain to be optimized independently - the core maintains high voltage for reliable write operations while peripherals operate at low voltage for power efficiency.
Solution Approach 2:
Different voltage levels are applied to different parts of the memory device based on their specific functional requirements. The memory core receives higher voltage to ensure stable transistor behavior during write operations, while peripheral circuits receive lower voltage to minimize power consumption. This local quality approach tailors voltage characteristics to the specific needs of each circuit region.
2Device complexity
If a single voltage level is used for the entire memory device, then circuit design is simplified, but write operations become unreliable at low voltage levels
Solution Approach 1:
The memory device is divided into two distinct voltage domains: a first voltage domain for the memory core circuitry operating at a higher voltage level, and a second voltage domain for peripheral circuits operating at a lower voltage level. This segmentation allows each domain to be optimized independently - the core maintains high voltage for reliable write operations while peripherals operate at low voltage for power efficiency.
Solution Approach 2:
The voltage parameter is changed differently across different regions of the memory device. The memory core operates at a first voltage level sufficient for reliable write operations, while peripheral circuits operate at a second, lower voltage level. This parameter change enables the system to achieve both reliability and power efficiency by optimizing voltage for each functional region.
3Reliability
If higher voltage is maintained at the memory core during write operations, then writeability is improved, but dynamic power consumption increases
Solution Approach 1:
The memory device is divided into two distinct voltage domains: a first voltage domain for the memory core circuitry operating at a higher voltage level, and a second voltage domain for peripheral circuits operating at a lower voltage level. This segmentation allows each domain to be optimized independently - the core maintains high voltage for reliable write operations while peripherals operate at low voltage for power efficiency.
Solution Approach 2:
The memory device alternates between different operational modes with different voltage configurations. During write operations, the memory core operates at a higher voltage level to ensure reliable data writing. During idle or read operations, the device can transition to a lower power state. This periodic action allows the system to consume higher power only when necessary for write operations.
Data Source
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AI summary
A write assist driver circuit is provided that assists a memory cell (e.g., volatile memory bit cell) in write operations to keep the voltage at the memory core sufficiently high for correct write operations, even when the supply voltage is lowered. The write assist driver circuit may be configured to provide a memory supply voltage VddM to a bit cell core during a standby mode of operation. In a write mode of operation, the write assist driver circuit may provide a lowered memory supply voltage VddMlower to the bit cell core as well as to at least one of the local write bitline (lwbl) and local write bitline bar (lwblb). Additionally, the write assist driver circuit may also provide a periphery supply voltage VddP to a local write wordline (lwwl), where VddP ≥ VddM > VddMlower.