Write Assist Circuit for Simultaneous Read-Write Memory Disturbance
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Solution Overview
Problem
Conventional two-port memories face a critical minimum operable power supply voltage issue due to write operation disturbances caused by simultaneous read operations, particularly when there is timing skew between word lines, leading to failed write operations and limited VDDmin.
Innovation Solution
A write assist circuit is introduced, comprising a word line detection circuit and a write assist cell with NMOS and PMOS transistors, which detects simultaneous assertion of word lines and transfers data from one bit line to another during overlapping write and read operations, reducing write disturbances and improving VDDmin.
Engineering Contradictions & Design Principles
Engineering Contradiction Analysis
1Productivity
If a write operation and read operation are performed simultaneously on a two-port memory, then memory throughput and productivity are improved, but write operation reliability deteriorates due to timing skew causing write data disturbance
Solution Approach 1:
The write assist circuit performs preliminary action by detecting the timing skew condition between read and write word lines before the write operation completes. When timing skew is detected (read word line asserted after write word line), the circuit proactively disables the write word line or modifies the write operation to prevent data disturbance, thereby maintaining write reliability while allowing simultaneous read-write operations to proceed
Solution Approach 2:
The write assist circuit acts as an intermediary between the read and write operations. It monitors the timing relationships between read word line (WLB) and write word line (WLA), and when timing skew is detected, it intervenes by controlling additional transistors to disable or modify the write operation, preventing the harmful interaction between simultaneous read and write operations on the same memory array
2Productivity
If simultaneous A-port write and B-port read access occur on the same row, then memory productivity is improved, but the minimum operable power supply voltage VDDmin increases due to write disturbance
Solution Approach 1:
The write assist circuit performs preliminary detection of the simultaneous read-write condition on the same row. When the condition is detected (through timing skew detection between WLB and WLA), the circuit proactively prevents the write operation that would cause disturbance, thereby maintaining stable VDDmin requirements while allowing high-speed simultaneous access operations
Solution Approach 2:
The write assist circuit applies preliminary anti-action by detecting the harmful condition (simultaneous read-write on same row with timing skew) and applying a counter-action to disable or modify the write operation before the disturbance can occur. This prevents the increase in VDDmin that would result from write disturbance, maintaining stable power requirements while enabling high-speed simultaneous access
Data Source
AI summary
A write assist cell includes a first pull-down circuit configured to transfer data from a first bit line to a second bit line during a write operation. The write assist cell further includes a second pull-down circuit configured to transfer data from a third bit line to a fourth bit line during a read operation, wherein the write operation and the read operation occur simultaneously. A memory device includes a memory array, the memory array comprises a first bit line and a second bit line. The memory device further includes a write assist cell connected to the memory array, wherein the write assist cell is configured to transfer data from the first bit line in a write operation to the second bit line in a read operation, and the write operation and the read operation occur simultaneously. The memory device further includes a multiplexer connected to the write assist cell.